AD9740 Analog Devices, AD9740 Datasheet - Page 6
AD9740
Manufacturer Part Number
AD9740
Description
Manufacturer
Analog Devices
Datasheet
1.AD9740.pdf
(32 pages)
Specifications of AD9740
Resolution (bits)
10bit
Dac Update Rate
210MSPS
Dac Settling Time
11ns
Max Pos Supply (v)
+3.6V
Single-supply
Yes
Dac Type
Current Out
Dac Input Format
Par
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9740
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9740ACP
Manufacturer:
ADI
Quantity:
329
Company:
Part Number:
AD9740ACPZ
Manufacturer:
AD
Quantity:
2 140
Part Number:
AD9740ACPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9740ACPZRL7
Manufacturer:
NXP
Quantity:
2 800
Part Number:
AD9740ACPZRL7
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9740ARU
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD9740ARUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Company:
Part Number:
AD9740ARUZ-RL7
Manufacturer:
AD
Quantity:
670
Company:
Part Number:
AD9740ARZ
Manufacturer:
Analog Devices Inc
Quantity:
135
AD9740
Parameter
1
2
3
DIGITAL SPECIFICATIONS
T
Table 3.
Parameter
DIGITAL INPUTS
CLK INPUTS
1
2
Measured single-ended into 50 Ω load.
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
Applicable to CLK+ and CLK− inputs when configured for differential or PECL clock input mode.
MIN
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
Input Setup Time (t
Input Hold Time (t
Latch Pulse Width (t
Input Voltage Range
Common-Mode Voltage
Differential Voltage
f
to T
CLOCK
0 dBFS Output
−6 dBFS Output
−12 dBFS Output
−18 dBFS Output
MAX
= 78 MSPS; f
2
, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, I
1
H
S
)
OUT
LPW
)
)
= 15.0 MHz to 18.2 MHz
DB0–DB9
CLOCK
IOUTA
IOUTB
OR
t
S
Figure 2. Timing Diagram
Rev. B | Page 6 of 32
t
PD
OUTFS
= 20 mA, unless otherwise noted.
0.1%
Min
2.1
−10
−10
2.0
1.5
1.5
0
0.75
0.5
t
t
ST
LPW
t
H
0.1%
Min
Typ
3
0
5
1.5
1.5
Typ
65
66
60
55
Max
0.9
+10
+10
3
2.25
Max
Unit
V
V
μA
μA
pF
ns
ns
ns
V
V
V
Unit
dBc
dBc
dBc
dBc