AD9740 Analog Devices, AD9740 Datasheet
AD9740
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AD9740 Summary of contents
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... The AD9740 offers exceptional ac and dc performance while supporting update rates up to 210 MSPS. The AD9740’s low power dissipation makes it well suited for portable and low power applications. Its power dissipation can be further reduced with a slight degradation in performance by lowering the full-scale current output ...
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... DAC Transfer Function ............................................................. 14 Analog Outputs .......................................................................... 14 Digital Inputs .............................................................................. 15 Clock Input.................................................................................. 15 DAC Timing................................................................................ 16 Power Dissipation....................................................................... 16 Applying the AD9740 ................................................................ 17 Differential Coupling Using a Transformer............................... 17 Differential Coupling Using an Op Amp................................ 18 Single-Ended, Unbuffered Voltage Output............................. 18 Single-Ended, Buffered Voltage Output Configuration........ 18 Power and Grounding Considerations, Power Supply Rejection...................................................................................... 19 Evaluation Board ...
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... Added Clock Input Section............................................................12 Added Figure 7 ................................................................................12 Edits to DAC Timing Section........................................................12 Edits to Sleep Mode Operation Section .......................................13 Edits to Power Dissipation Section...............................................13 Renumbered Figures 8 to 26..........................................................13 Added Figure 11 ..............................................................................13 Added Figures 27 to 35...................................................................21 Updated Outline Dimensions........................................................26 5/02—Revision 0: Initial Version Rev Page AD9740 ...
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... AD9740 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current 2 Output Compliance Range ...
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... CLOCK OUT OUTFS f = 210 MSPS MHz; I CLOCK OUT OUTFS = 20 mA, differential transformer coupled output, 50 Ω doubly OUTFS = Rev Page AD9740 Min Typ Max Unit 210 MSPS pV-s 2 pA/√Hz 30 pA/√ ...
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... AD9740 Parameter Multitone Power Ratio (8 Tones at 400 kHz Spacing MSPS 15.0 MHz to 18.2 MHz CLOCK OUT 0 dBFS Output −6 dBFS Output −12 dBFS Output −18 dBFS Output 1 Measured single-ended into 50 Ω load. 2 Output noise is measured with a full-scale output set with no conversion activity measure of the thermal noise only. ...
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... JA +3.9 V 28-Lead TSSOP +3.9 V θ = 67.7°C/W JA +0.3 V 32-Lead LFCSP +0.3 V θ = 32.5°C Thermal impedance measurements were taken on a 4-layer board in still air, +3 accordance with EIA/JESD51-7. +3.9 V +3.9 V DVDD + 0.3 V DVDD + 0.3 V AVDD + 0.3 V AVDD + 0.3 V CLKVDD + 0.3 V 150 °C +150 °C 300 °C Rev Page AD9740 1 ...
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... Clock Input. Data latched on positive edge of clock. Differential Clock Input. Differential Clock Input. Clock Supply Voltage (3.3 V). Clock Common. Rev Page DB3 ADJ PIN 1 DB2 2 23 REFIO INDICATOR DVDD 3 22 ACOM AD9740 DB1 4 21 IOUTA DB0 5 20 IOUTB TOP VIEW ACOM (Not to Scale AVDD NC 8 ...
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... LATCHES DIGITAL DATA TEKTRONIX AWG-2021 WITH OPTION 4 Figure 5. Basic AC Characterization Test Setup (SOIC/TSSOP Packages) Rev Page MINI-CIRCUITS T1-1T ROHDE & SCHWARZ FSEA30 SPECTRUM ANALYZER 50Ω 50Ω *AWG2021 CLOCK RETIMED SO THAT THE DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. AD9740 ...
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... AD9740 TYPICAL PERFORMANCE CHARACTERISTICS 95 210MSPS (LFCSP) 90 125MSPS 65MSPS 70 125MSPS (LFCSP 210MSPS (MHz) OUT Figure 6. SFDR vs dBFS OUT (MHz) OUT Figure 7. SFDR vs MSPS OUT 95 90 0dBFS 85 80 ...
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... LFCSP 78MSPS –20 –15 –10 –5 A (dBFS) OUT Figure 15. Dual-Tone IMD vs OUT OUT CLOCK 256 512 768 CODE Figure 16. Typical INL 256 512 768 CODE Figure 17. Typical DNL AD9740 0 /7 1024 1024 ...
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... CLOCK f = 15.0MHz OUT1 f = 15.4MHz OUT2 f = 15.8MHz OUT3 f = 16.2MHz OUT4 SFDR = 72dBc AMPLITUDE = 0dBFS FREQUENCY (MHz) Figure 21. Four-Tone SFDR ACOM AD9740 DIFF OUTA IOUTA IOUTA IOUTB IOUTB V OUTB R MODE LOAD 50Ω = 78MSPS 78MSPS 31 36 – V OUTB V OUTA ...
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... OUTFS REF REFERENCE OPERATION The AD9740 contains an internal 1.2 V band gap reference. The internal reference cannot be disabled, but can be easily overridden by an external reference with no effect on performance. Figure 23 shows an equivalent circuit of the band gap reference. REFIO serves as either an output or an input depending on whether the internal or an external reference is used ...
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... REFERENCE AD9740 CONTROL AMPLIFIER Figure 25. External Reference Configuration REFERENCE CONTROL AMPLIFIER The AD9740 contains a control amplifier that is used to regulate the full-scale output current The control amplifier is OUTFS configured as a V-I converter, as shown in Figure 24, so that its current output determined by the ratio of the V ...
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... Because the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer allows the AD9740 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ ...
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... SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 Ω AVDD. This digital input also contains an active pull-down circuit that ensures that the AD9740 remains enabled if this input is left disconnected. The AD9740 takes less than power down and approximately 5 μs to power back up. POWER DISSIPATION ...
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... CLKVDD CLOCK APPLYING THE AD9740 Output Configurations The following sections illustrate some typical output configurations for the AD9740. Unless otherwise noted assumed that I requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration can consist of either an RF transformer or a differential op amp configuration ...
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... In this case, AVDD, which is the positive analog supply for both the AD9740 and the op amp, is also used to level shift the differential output of the AD9740 to midsupply (that is, AVDD/2). The AD8041 is a suitable op amp for this application. ...
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... OUTFS is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise occurs over the spectrum from tens of kilohertz to several megahertz. The PSRR vs. frequency of the AD9740 AVDD supply over this frequency range is shown in Figure 37 ...
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... The digital inputs are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9740 with either the internal or external reference or to exercise the power-down feature. DB13X ...
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... WHT R2 10kΩ JP2 MODE REF TP3 C1 C2 WHT 0.1μF 0.1μF C11 R1 0.1μF AVDD 2kΩ IY Figure 40. SOIC Evaluation Board—Output Signal Conditioning Rev Page AD9740 JP10 R11 IOUTA 10kΩ C13 OPT JP8 OPT ...
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... AD9740 Figure 41. SOIC Evaluation Board—Primary Side Figure 42. SOIC Evaluation Board—Secondary Side Rev Page ...
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... Figure 43. SOIC Evaluation Board—Ground Plane Figure 44. SOIC Evaluation Board—Power Plane Rev Page AD9740 ...
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... AD9740 Figure 45. SOIC Evaluation Board Assembly—Primary Side Figure 46. SOIC Evaluation Board Assembly—Secondary Side Rev Page ...
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... DB8X 14 13 DB7X 16 15 DB6X 18 17 DB5X 20 19 DB4X 22 21 DB3X 24 23 DB2X 26 25 DB1X 28 27 DB0X JP3 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CKEXT AD9740 CKEXTX ...
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... CLK 13 20 CLKB IB CLKB 14 19 CCOM ACOM1 15 18 CMODE AVDD 16 CMODE 17 MODE AVDD1 AD9740LFCSP TP7 R30 10kΩ WHT CVDD JP1 MODE Figure 48. LFCSP Evaluation Board Schematic—Output Signal Conditioning CLKB JP2 CKEXT CLK AVDD C17 0.1μF SLEEP TP11 WHT R29 10kΩ ...
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... Figure 50. LFCSP Evaluation Board Layout—Primary Side Figure 51. LFCSP Evaluation Board Layout—Secondary Side Rev Page AD9740 ...
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... AD9740 Figure 52. LFCSP Evaluation Board Layout—Ground Plane Figure 53. LFCSP Evaluation Board Layout—Power Plane Rev Page ...
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... Figure 54. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 55. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev Page AD9740 ...
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... AD9740 OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 0.19 SEATING 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 56. 28-Lead Thin Shrink Small Outline Package [TSSOP] (RU-28) Dimensions shown in millimeters 18.10 (0.7126) 17.70 (0.6969 7.60 (0.2992) 7.40 (0.2913 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) SEATING 0.51 (0.0201) ...
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... AD9740ARUZ −40°C to +85°C 1 AD9740ARUZRL7 −40°C to +85°C AD9740ACP −40°C to +85°C AD9740ACPRL7 −40°C to +85°C 1 AD9740ACPZ −40°C to +85°C 1 AD9740ACPZRL7 −40°C to +85°C AD9740-EB AD9740ACP-PCB Pb-free part. 5.00 BSC SQ 0.60 MAX 24 0 ...
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... AD9740 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02911–0–12/05(B) Rev Page ...