AD5381 Analog Devices, AD5381 Datasheet - Page 10

• Manufacturer Part Number: AD5381
• Description: 40-Channel 12-Bit 3 V/5 V Single-Supply Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5381

• Resolution (bits): 12bit
• Dac Update Rate: 167kSPS
• Dac Settling Time: 6µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Par,Ser,SPI

AD5381
I
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
unless otherwise noted.
Table 7.
Parameter
F
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
2
Guaranteed by design and characterization, not production tested.
See Figure 6.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
SCL’s falling edge.
C
SCL
b
3
SDA
C SERIAL INTERFACE TIMING
SCL
b
is the total capacitance, in pF, of one bus line. t
1, 2
t
9
CONDITION
START
Limit at T
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
300
0
300
20 + 0.1 C
400
t
4
t
b
MIN
3
4
, T
MAX
t
10
R
and t
t
6
Figure 6. I
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
F
are measured between 0.3 DVDD and 0.7 DVDD.
2
C-Compatible Serial Interface Timing Diagram
t
2
Description
SCL clock frequency
SCL cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Capacitive load for each bus line
Rev. B | Page 10 of 40
HIGH
LOW
HD,STA
SU,DAT
HD,DAT
HD,DAT
SU,STA
SU,STO
BUF
R
R
F
F
F
F
, rise time of SCL and SDA when receiving
, rise time of SCL and SDA when receiving (CMOS compatible)
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
, bus free time between a STOP and a START condition
, SCL low time
, SCL high time
t
, setup time for repeated start
, stop condition setup time
, start/repeated start condition hold time
, data setup time
11
, data hold time
, data hold time
t
5
IH
min of the SCL signal) in order to bridge the undefined region of
CONDITION
REPEATED
START
t
7
t
4
t
1
MIN
to T
MAX
,
CONDITION
STOP
t
8