AD5060 Analog Devices, AD5060 Datasheet - Page 17

• Manufacturer Part Number: AD5060
• Manufacturer: Analog Devices

Specifications of AD5060

• Resolution (bits): 16bit
• Dac Update Rate: 250kSPS
• Dac Settling Time: 4µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

POWER-DOWN MODES
The AD5060 features four operating modes, and the AD5040
features three operating modes. These modes are software pro-
grammable by setting two bits in the control register (Bit DB17
and Bit DB16 in the AD5060 and Bit DB15 and Bit DB14 in the
AD5040). Table 6 and Table 7 show how the state of the bits
corresponds to the operating mode of the two devices.
Table 6. Operating Modes for the AD5060
DB17
0
0
1
1
Table 7. Operating Modes for the AD5040
DB15
0
0
1
1
In both the AD5060 and the AD5040, when the two most
significant bits are set to 0, the part has normal power
consumption. However, for the three power-down modes of the
AD5060 and the two power down modes of the AD5040, the
supply current falls to less than 1μA at 5 V (65 nA at 3 V). Not
only does the supply current fall, but the output stage is also
internally switched from the output of the amplifier to a resistor
network of known values. This is advantageous because the
output impedance of the part is known while the part is in
power-down mode. The output is connected internally to GND
through a 1 kΩ resistor (AD5060 only) or a 100 kΩ resistor, or
it is left open-circuited (three-stated). The output stage is
illustrated in Figure 44.
The bias generator, the DAC core, and other associated linear
circuitry are all shut down when power-down mode is
activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 2.5 μs for V
see Figure 29.
AD5040/
AD5060
DAC
Figure 44. Output Stage During Power-Down
DB16
0
1
0
1
DB14
0
1
0
1
DD
POWER-DOWN
CIRCUITRY
= 5 V, and 5 μs for V
Normal operation
Power-down modes:
Operating Mode
Operating Mode
Normal operation
Power-down modes:
OUTPUT
BUFFER
3-state
100 kΩ to GND
1 kΩ to GND
3-state
100 kΩ to GND
See Software Reset section
RESISTOR
NETWORK
DD
= 3 V;
V
OUT
Rev. A | Page 17 of 24
MICROPROCESSOR INTERFACING
AD5040/AD5060 to ADSP-2101/ADSP-2103 Interface
Figure 45 shows a serial interface between the AD5040/AD5060
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP-2101/ADSP-2103 sport is pro-
grammed through the SPORT control register and should be
configured for internal clock operation, active low framing, and
16-bit word length. Transmission is initiated by writing a word
to the Tx register after the SPORT has been enabled.
AD5040/AD5060 to 68HC11/68L11 Interface
Figure 46 shows a serial interface between the AD5040/
AD5060 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK pin of the AD5040/AD5060,
while the MOSI output drives the serial data line of the DAC.
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface require that the
68HC11/68L11 be configured so that its CPOL bit is 0 and its
CPHA bit is 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured where its CPOL bit is 0 and its CPHA bit is 1, data
appearing on the MOSI output is valid on the falling edge of
SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit
bytes with only 8 falling clock edges occurring in the transmit
cycle. Data is transmitted MSB first. In order to load data to the
AD5040/AD5060, PC7 is left low after the first eight bits are
transferred, and a second serial write operation is performed to
the DAC. PC7 is taken high at the end of this procedure.
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 45. AD5040/AD5060 to ADSP-2101/ADSP-2103 Interface
ADSP-2103
ADSP-2101/
68HC11/
68L11
Figure 46. AD5040/AD5060 to 68HC11/68L11 Interface
1
1
SCLK
MOSI
TFS
SCK
PC7
DT
AD5040/AD5060
SYNC
DIN
SCLK
SYNC
SCLK
DIN
AD5060
AD5040/
AD5060
AD5040/
1
1