AD5373 Analog Devices, AD5373 Datasheet - Page 15

• Manufacturer Part Number: AD5373
• Description: 32-Channel, 14-Bit, Serial Input, Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5373

• Resolution (bits): 14bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

THEORY OF OPERATION
DAC ARCHITECTURE
The AD5372/AD5373 contain 32 DAC channels and 32 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit (AD5372) or 14-bit (AD5373)
resistor-string DAC followed by an output buffer amplifier.
The resistor-string section is simply a string of resistors (of
equal value) from VREF0 or VREF1 to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit
(AD5372) or 14-bit (AD5373) binary digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off before being fed into the output amplifier.
Table 7. AD5372/AD5373 Registers
Register Name
X1A (Group) (Channel)
X1B (Group) (Channel)
M (Group) (Channel)
C (Group) (Channel)
X2A (Group) (Channel)
X2B (Group) (Channel)
DAC (Group) (Channel)
OFS0
OFS1
Control
A/B Select 0
A/B Select 1
A/B Select 2
A/B Select 3
Table 8. AD5372/AD5373 Input Register Default Values
Register Name
X1A, X1B
M
C
OFS0, OFS1
Control
A/B Select 0 to A/B Select 3
Word Length
in Bits
16 (14)
16 (14)
16 (14)
16 (14)
16 (14)
16 (14)
14
14
3
8
8
8
8
Description
Input Data Register A, one for each DAC channel.
Input Data Register B, one for each DAC channel.
Gain trim registers, one for each DAC channel.
Offset trim registers, one for each DAC channel.
Output Data Register A, one for each DAC channel. These registers store the final, calibrated
DAC data after gain and offset trimming. They are not readable or directly writable.
Output Data Register B, one for each DAC channel. These registers store the final, calibrated
DAC data after gain and offset trimming. They are not readable or directly writable.
Data registers from which the DACs take their final input data. The DAC registers are updated
from the X2A or X2B registers. They are not readable or directly writable.
Offset DAC 0 data register: sets offset for Group 0.
Offset DAC 1 data register: sets offset for Group 1 to Group 3.
Bit 2 = A/B.
Bit 1 = enable thermal shutdown.
Bit 0 = software power-down.
Each bit in this register determines whether a DAC in Group 0 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
Each bit in this register determines whether a DAC in Group 1 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
Each bit in this register determines whether a DAC in Group 2 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
Each bit in this register determines whether a DAC in Group 3 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
AD5372 Default Value
0x5554
0xFFFF
0x8000
0x1555
0x00
0x00
0 = global selection of X1A input data registers.
1 = global selection of X1B input data registers.
0 = disable thermal shutdown.
1 = enable thermal shutdown.
0 = software power-up.
1 = software power-down.
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The output amplifier multiplies the DAC output voltage by 4.
The nominal output span is 12 V with a 3 V reference and 20 V
with a 5 V reference.
CHANNEL GROUPS
The 32 DAC channels of the AD5372/AD5373 are arranged into
four groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 3 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.
AD5373 Default Value
0x1555
0x3FFF
0x2000
0x1555
0x00
0x00
AD5372/AD5373