AD5373 Analog Devices, AD5373 Datasheet - Page 10

• Manufacturer Part Number: AD5373
• Description: 32-Channel, 14-Bit, Serial Input, Voltage-Output DAC
• Manufacturer: Analog Devices

Specifications of AD5373

• Resolution (bits): 14bit
• Dac Update Rate: 540kSPS
• Dac Settling Time: 20µs
• Max Pos Supply (v): +16.5V
• Single-supply: No
• Dac Type: Voltage Out
• Dac Input Format: Ser,SPI

AD5372/AD5373
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
0
1
2
42 to 45, 47 to 50, 21 to 24,
26 to 33, 37 to 40, 60 to 62,
3, 5 to 8
4
9 to 15, 19, 20
16, 35
17, 36
18
25
34
41
46
51, 58
52, 57
53
54
55
INDICATOR
SIGGND3
NOTES
1. NC = NO CONNECT.
2. THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP) HAS AN EXPOSED PAD
VOUT27
VOUT28
VOUT29
VOUT30
VOUT31
RESET
ON THE UNDERSIDE. CONNECT THE EXPOSED PAD TO V
BUSY
PIN 1
V
NC
NC
NC
NC
NC
NC
NC
DD
10
12
13
14
15
16
11
1
2
3
4
5
6
7
8
9
Figure 7. 64-Lead LFCSP Pin Configuration
AD5372/AD5373
(Not to Scale)
TOP VIEW
Mnemonic
EPAD
RESET
BUSY
VOUT0 to
VOUT31
SIGGND3
NC
V
V
VREF1
SIGGND1
SIGGND2
VREF0
SIGGND0
DGND
DV
SYNC
SCLK
SDI
DD
SS
CC
Description
Exposed Pad. The lead frame chip scale package (LFCSP) has an exposed pad on the
underside. Connected the exposed pad to V
Digital Reset Input.
Digital Input/Open-Drain Output. BUSY is open drain when an output. See the BUSY and
LDAC Functions section for more information.
DAC Outputs. Buffered analog outputs for each of the 32 DAC channels. Each analog output is
capable of driving an output load of 10 kΩ to ground. Typical output impedance of these
amplifiers is 0.5 Ω.
Reference Ground for DAC 24 to DAC 31. VOUT24 to VOUT31 are referenced to this voltage.
No Connect.
Positive Analog Power Supply; 9 V to 16.5 V for specified performance. These pins should be
decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins should
be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors.
Reference Input for DAC 8 to DAC 31. This reference voltage is referred to AGND.
Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.
Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.
Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.
Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.
Ground for All Digital Circuitry. The DGND pins should be connected to the DGND plane.
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 μF ceramic
capacitors and 10 μF capacitors.
Active Low Input. This is the frame synchronization signal for the serial interface.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin
operates at clock speeds up to 50 MHz.
Serial Data Input. Data must be valid on the falling edge of SCLK.
SS
.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VOUT5
VOUT4
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
VREF0
VOUT23
VOUT22
VOUT21
VOUT20
V
V
SIGGND2
VOUT19
SS
DD
Rev. C | Page 10 of 28
SIGGND3
NC = NO CONNECT
VOUT27
VOUT28
VOUT29
VOUT30
VOUT31
RESET
BUSY
V
NC
NC
NC
NC
NC
NC
NC
DD
10
11
12
13
14
15
16
1
2
4
5
6
7
8
3
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 8. 64-Lead LQFP Pin Configuration
PIN 1
INDICATOR
SS
.
AD5372/AD5373
(Not to Scale)
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VOUT5
VOUT4
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
VREF0
VOUT23
VOUT22
VOUT21
VOUT20
V
V
SIGGND2
VOUT19
SS
DD