AD5066 Analog Devices, AD5066 Datasheet - Page 18

• Manufacturer Part Number: AD5066
• Description: Fully Accurate, 16-Bit, UnBuffered VOUT Quad SPI Interface, 2.7 V to 5.5 V nanoDAC in a TSSOP
• Manufacturer: Analog Devices

Specifications of AD5066

• Resolution (bits): 16bit
• Dac Settling Time: 12µs
• Max Pos Supply (v): +5.5V
• Single-supply: Yes
• Dac Type: Unbuffered Vout
• Dac Input Format: Ser,SPI

AD5066
CLEAR CODE REGISTER
The AD5066 has a hardware CLR pin that is an asynchronous
clear input. The CLR input is falling edge sensitive. Bringing the
CLR line low clears the contents of the input register and the
DAC registers to the data contained in the user-configurable
CLR register and sets the analog outputs accordingly (see
Table 11). This function can be used in system calibration to
load zero scale, midscale, or full scale to all channels together.
These clear code values are user-programmable by setting two
bits, Bit DB1 and Bit DB0, in the control register (see Table 11).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 7).
Table 11. Clear Code Register
DB1 (CR1)
0
0
1
1
The part exits clear code mode on the 32
next write to the part. If CLR is activated during a write
sequence, the write is aborted.
The CLR pulse activation time (the falling edge of CLR to when
the output starts to change) is typically 10.6 µs. See Table 13 for
contents of the input shift register during the loading clear code
register operation.
LDAC FUNCTION
Hardware LDAC Pin
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin, as shown in Figure 2. There are two
methods of using the hardware LDAC pin: synchronously
( LDAC permanently low) and asynchronously ( LDAC pulsed).
Table 13. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
DB31 to DB28
X
Don’t cares
Table 14. 32-Bit Input Shift Register Contents for LDAC
MSB
DB31
to DB28
X
Don’t cares
DB27
0
Command bits (C3 to C0)
DB0 (CR0)
0
1
0
1
DB27
0
DB26
1
Command bits (C3 to C0)
DB26
1
DB25
1
Clears to Code
0x0000
0x8000
0xFFFF
No operation
DB25
0
DB24
0
nd
falling edge of the
DB24
1
DB23 to DB20
X
Address bits (A3 to A0)—don’t cares
DB23
X
Overwrite Function
Rev. A | Page 18 of 24
Address bits (A3 to A0)
DB22
X
Synchronous LDAC : LDAC is held permanently low. After new
data is read, the DAC registers are updated on the falling edge
of the 32
Asynchronous LDAC : LDAC is held high then pulsed low to
update. The outputs are not updated at the same time that the
input registers are written to. When LDAC is pulsed low, the
DAC registers are updated with the contents of the input
registers.
Command 0001, 0010 and 0011 (see Table 7) update the DAC
Register/Registers, regardless of the level of the LDAC pin
Software LDAC Function
Writing to the DAC using Command 0110 loads the 4-bit
LDAC register (DB3 to DB0). The default for each channel is
0; that is, the LDAC pin works normally. Setting the bits to 1
updates the DAC channel regardless of the state of the hardware
LDAC pin, so that it effectively sees the hardware LDAC pin
as being tied low (see Table 12 for the LDAC register mode of
operation.) This flexibility is useful in applications where the
user wants to simultaneously update select channels while the
remainder of the channels are synchronously updating.
Table 12. Load LDAC
LDAC Bits
(DB3 to
DB0)
0
1
1
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 14). Setting the LDAC
bits (DB0 to DB3) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware LDAC pin.
X = don’t care.
DB21
X
nd
SCLK pulse, provided LDAC is held low.
DB4
to DB19
X
Don’t cares
LDAC
Pin
1/0
X
DB20
X
1
LDAC Operation
Determined by LDAC pin
DAC channels update, overrides the LDAC
pin; DAC channels see LDAC as 0
Register
DB2 to DB19
X
Don’t cares
DB3
DAC D
Setting LDAC bit to 1 override LDAC pin
DB2
DAC C
DB1
1/0
Clear code register
DB1
DAC B
(CR1 to CR0)
LSB
DB0
1/0
LSB
DB0
DAC A