AD9125 Analog Devices, AD9125 Datasheet - Page 44

• Manufacturer Part Number: AD9125
• Manufacturer: Analog Devices

Specifications of AD9125

• Resolution (bits): 16bit
• Dac Update Rate: 1GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: Par

AD9125
Interfacing to Modulators
The AD9125 interfaces to the ADL537x family of modulators
with a minimal number of components. An example of the
recommended interface circuitry is shown in Figure 73.
The baseband inputs of the ADL537x family require a dc bias
of 500 mV. The nominal midscale output current on each output
of the DAC is 10 mA (½ the full-scale current). Therefore, a
single 50 Ω resistor to ground from each DAC output results in
the desired 500 mV dc common-mode bias for the inputs to the
ADL537x. The signal level can be reduced through the addition
of the load resistor in parallel with the modulator inputs. The
peak-to-peak voltage swing of the transmitted signal is
BASEBAND FILTER IMPLEMENTATION
Most applications require a baseband anti-imaging filter between
the DAC and the modulator to filter out Nyquist images and
broadband DAC noise. The filter can be inserted between the
I-V resistors at the DAC output and the signal-level setting resistor
across the modulator input. This configuration establishes the
input and output impedances for the filter.
Figure 75 shows a fifth-order low-pass filter. A common-mode
choke is used between the I-V resistors and the remainder of
the filter. This removes the common-mode signal produced by
the DAC and prevents the common-mode signal from being
converted to a differential signal, which can appear as unwanted
spurious signals in the output spectrum. Splitting the first filter
capacitor into two and grounding the center point creates a
common-mode low-pass filter, providing additional common-
mode rejection of high frequency signals. A purely differential
filter can pass common-mode signals.
Figure 73. Typical Interface Circuitry Between the AD9125 and the ADL537x
V
SIGNAL
AD9125
IOUT1P
IOUT1N
IOUT2N
IOUT2P
=
I
FS
×
67
66
59
58
[
[
2
2
R
R
×
×
R
R
Family of Modulators
50Ω
50Ω
BQN
50Ω
50Ω
BQP
R
BIP
BIN
R
B
B
×
+
R
R
L
L
]
]
100Ω
100Ω
R
R
LQ
LI
AD9125
Figure 75. DAC Modulator Interface with Fifth-Order, Low Pass Filter
IBBP
IBBN
QBBN
QBBP
ADL537x
50Ω
50Ω
2pF
Rev. 0 | Page 44 of 56
33nH
33nH
22pF
22pF
56nH
56nH
DRIVING THE ADL5375-15
The ADL5375-15 is the version of the
input baseband bias levels of 1500 mV. Because the ADL5375-15
requires a 1500 mV dc bias, it requires a slightly more complex
interface than most other Analog Devices, Inc., modulators. The
DAC output must be level-shifted from a 500 mV dc bias to the
1500 mV dc bias. Level-shifting can be achieved with a purely
passive network, as shown in Figure 74. In this network, the
dc bias of the DAC remains at 500 mV while the input to the
ADL5375-15 is 1500 mV. This passive level-shifting network
introduces approximately 2 dB of loss in the ac signal.
REDUCING LO LEAKAGE AND UNWANTED
SIDEBANDS
Analog quadrature modulators can introduce unwanted signals at
the LO frequency due to dc offset voltages in the I and Q baseband
inputs, as well as feedthrough paths from the LO input to the
output. The LO feedthrough can be nulled by applying the correct
dc offset voltages at the DAC output. This can be done using the
auxiliary DACs (Register 0x42, Register 0x43, Register 0x46, and
Register 0x47) or by using the digital dc offset adjustments
(Register 0x3C through Register 0x3F).
The advantage of using the auxiliary DACs is that none of the
main DAC dynamic range is used to perform the dc offset
adjustment. However, the disadvantage is that the common-
mode level of the output signal changes as a function of the
auxiliary DAC current. The opposite is true when the digital
offset adjustment is used.
Good sideband suppression requires both gain and phase
matching of the I and Q signals. The I phase adjust
(Register 0x38 and Register 0x39), Q phase adjust (Register
0x3A and Register 0x3B), I DAC FS adjust (Register 0x40 and
Register 0x41), and Q DAC FS adjust (Register 0x44 and
Register 0x45) registers can be used to calibrate I and Q
transmit paths to optimize the sideband suppression.
AD9125
Figure 74. Passive Level-Shifting Network for Biasing ADL5375-15
3pF
6pF
IOUT1N
IOUT2N
IOUT1P
IOUT2P
3pF
140Ω
67
66
59
58
ADL537x
45.3Ω
45.3Ω
45.3Ω
45.3Ω
R
R
R
R
BQN
BQP
BIN
BIP
R
R
R
R
1kΩ
1kΩ
1kΩ
1kΩ
SQN
SQP
SIN
SIP
3480Ω
3480Ω
3480Ω
3480Ω
R
R
R
R
LQN
LQP
LIP
LIN
ADL5375
5V
5V
21
22
10
9
ADL5375-15
IBBP
IBBN
QBBN
QBBP
that offers an