AD5421 Analog Devices, AD5421 Datasheet - Page 22

• Manufacturer Part Number: AD5421
• Description: 16-Bit, Serial Input, Loop-Powered, 4mA to 20mA DAC
• Manufacturer: Analog Devices

Specifications of AD5421

• Resolution (bits): 16bit
• Dac Settling Time: 50µs
• Max Pos Supply (v): +52V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: SPI

AD5421
ON-CHIP ADC
The AD5421 contains an on-chip ADC used to measure and
feed back to the fault register either the temperature of the die
or the voltage between the V
input bit (Bit D8) of the control register selects the parameter
to be converted. A conversion is initiated with command byte
00001000 (necessary only if auto fault readback is disabled). This
command byte powers on the ADC and performs the conversion.
A read of the fault register returns the conversion result. If auto
readback of the fault register is required, the ADC must first be
powered up by setting the on-chip ADC bit (Bit D7) of the
control register.
Because the FAULT pin can go high for as long as 30 μs, care is
required when performing a die temperature measurement after
a readback of the V
VOLTAGE REGULATOR
The on-chip voltage regulator provides a regulated voltage out-
put to supply the AD5421 and the remainder of the transmitter
circuitry. The output voltage range is from 1.8 V to 12 V and is
selected by the states of three digital input pins (see Table 10).
The regulator output is accessed at the REG
Table 10. Setting the Voltage Regulator Output
REG_SEL2
COM
COM
COM
COM
DV
DV
DV
LOOP CURRENT SLEW RATE CONTROL
The rate of change of the loop current can be controlled by
connecting an external capacitor between the C
COM. This reduces the rate of change of the loop current.
The output resistance of the DAC (R
C
response of the loop current (see Figure 44).
SLEW
DD
DD
DD
capacitor generate a time constant that determines the
REG_SEL1
COM
COM
DV
DV
COM
COM
DV
R
DD
DD
DD
DAC
Figure 44. Slew Capacitor Circuit
LOOP
voltage.
C
C
IN
SLEW
LOOP
REG_SEL0
COM
DV
COM
DV
COM
DV
COM
CIRCUITRY
DD
DD
DD
V-TO-I
and COM pins. The select ADC
DAC
) together with the
LOOP–
Regulated Output
Voltage (V)
1.8
2.5
3.0
3.3
5.0
9.0
12.0
OUT
pin.
IN
pin and
Rev. C | Page 22 of 36
The resistance of the DAC is typically 15.22 kΩ for the 4 mA
to 20 mA and 3.8 mA to 21 mA loop current ranges. The DAC
resistance changes to 16.11 kΩ when the 3.2 mA to 24 mA loop
current range is selected.
The time constant of the circuit is expressed as
Taking five time constants as the required time to reach the final
value, C
as follows:
where:
t is the desired time for the output current to reach its final
value.
R
16.11 kΩ, depending on the selected loop current range.
For a response time of 5 ms,
For a response time of 10 ms,
The responses for both of these configurations are shown
in Figure 45.
The C
FSK signaling. The HART signal must be ac-coupled to the C
input. The capacitor through which the HART signal is coupled
must be considered in the preceding calculations, where the
total capacitance is C
the HART Communications section.
DAC
τ = R
is the resistance of the DAC core, either 15.22 kΩ or
C
C
C
IN
SLEW
SLEW
SLEW
SLEW
6
5
4
3
2
1
0
pin can also be used as a coupling input for HART
–2
Figure 45. 4 mA to 20 mA Step with Slew Rate Control
DAC
can be determined for a desired response time, t,
=
=
=
C
× C
SLEW
5
5
5
×
×
×
SLEW
2
10
5
= 68nF
15
15
t
R
ms
ms
C
DAC
,
,
SLEW
SLEW
220
220
6
+ C
= 133nF
≈
≈
C
133
68
SLEW
HART
TIME (ms)
nF
nF
10
= 267nF
. For more information, see
14
Data Sheet
18
22
IN