AD5421 Analog Devices, AD5421 Datasheet - Page 11

• Manufacturer Part Number: AD5421
• Description: 16-Bit, Serial Input, Loop-Powered, 4mA to 20mA DAC
• Manufacturer: Analog Devices

Specifications of AD5421

• Resolution (bits): 16bit
• Dac Settling Time: 50µs
• Max Pos Supply (v): +52V
• Single-supply: Yes
• Dac Type: Current Out
• Dac Input Format: SPI

Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 8. Pin Function Descriptions
TSSOP
1
2
3
4
5
6
7
8
9
10
11, 12
ALARM_CURRENT_DIRECTION
Pin No.
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE SAME
POTENTIAL AS THE COM PIN AND TO A COPPER PLANE FOR
OPTIMUM THERMAL PERFORMANCE.
LFCSP
29
30
31
32
1
2
3
5
6
7
8, 10
R
Figure 4. TSSOP Pin Configuration
RANGE0
RANGE1
INT
IODV
FAULT
SYNC
LDAC
SCLK
/R
DV
SDIN
COM
COM
SDO
EXT
DD
DD
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Mnemonic
IODV
SDO
SCLK
SYNC
SDIN
LDAC
FAULT
DV
ALARM_
CURRENT_
DIRECTION
R
RANGE0,
RANGE1
INT
(Not to Scale)
DD
/R
AD5421
TOP VIEW
DD
EXT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Description
Digital Interface Supply Pin. Digital thresholds are referenced to the voltage applied to this pin. A
voltage from 1.71 V to 5.5 V can be applied to this pin.
Serial Data Output. Used to clock data from the input shift register. Data is clocked out on the
rising edge of SCLK and is valid on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This
input operates at clock speeds up to 30 MHz.
Frame Synchronization Input, Active Low. This is the frame synchronization signal for the serial
interface. When SYNC is low, data is transferred on the falling edge of SCLK. The input shift
register data is latched on the rising edge of SYNC .
Serial Data Input. Data must be valid on the falling edge of SCLK.
Load DAC Input, Active Low. This pin is used to update the DAC register and, consequently, the
output current. If LDAC is tied permanently low, the DAC register is updated on the rising edge
of SYNC . If LDAC is held high during the write cycle, the input register is updated, but the output
update is delayed until the falling edge of LDAC . The LDAC pin should not be left unconnected.
Fault Alert Output Pin, Active High. This pin is asserted high when a fault is detected. Detectable
faults are loss of SPI interface control, communication error (PEC), loop current out of range,
insufficient loop voltage, and overtemperature. For more information, see the Fault Alerts
section.
3.3 V Digital Power Supply Output. This pin should be decoupled to COM with 100 nF and 4.7 µF
capacitors.
Alarm Current Direction Select. This pin is used to select whether the alarm current is upscale
(22.8 mA/24 mA) or downscale (3.2 mA). Connecting this pin to DV
current (22.8 mA/24 mA); connecting this pin to COM selects a downscale alarm current (3.2 mA).
For more information, see the Power-On Default section.
Current Setting Resistor Select. When this pin is connected to DV
resistor is selected. When this pin is connected to COM, the external current setting resistor is
selected. An external resistor can be connected between the R
Digital Input Pins. These two pins select the loop current range (see the Loop Current Range
Selection section).
REG
REG
DRIVE
V
LOOP–
R
R
C
REFOUT1
REFOUT2
REFIN
REG_SEL0
REG_SEL1
REG_SEL2
LOOP
EXT2
EXT1
IN
OUT
IN
Rev. C | Page 11 of 36
ALARM CURRENT DIRECTION
NOTES
1. NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE
SAME POTENTIAL AS THE COM PIN AND TO A COPPER
PLANE FOR OPTIMUM THERMAL PERFORMANCE.
R
RANGE 0
INT
Figure 5. LFCSP Pin Configuration
FAULT
LDAC
DV
/R
SDIN
COM
EXT
DD
1
2
3
4
5
6
7
8
EXT1
DD
PIN 1
INDICATOR
(Not to Scale)
and R
AD5421
TOP VIEW
DD
, the internal current setting
selects an upscale alarm
EXT2
pins.
24 V
23 LOOP–
22 R
21 R
20 C
19 REFOUT1
18 REFOUT2
17 REFIN
AD5421
LOOP
EXT2
EXT1
IN