AD5755 Analog Devices, AD5755 Datasheet - Page 30

• Manufacturer Part Number: AD5755
• Description: Quad Channel, 16-Bit, Serial Input,
• Manufacturer: Analog Devices

Specifications of AD5755

• Resolution (bits): 16bit
• Dac Update Rate: 91kSPS
• Dac Settling Time: 11µs
• Max Pos Supply (v): +33V
• Single-supply: No
• Dac Type: I or V Out
• Dac Input Format: SPI

AD5755
Even though the output ranges are not enabled, the default
output range is 0 V to 5 V, and the clear code register is loaded
with all zeros. This means that if the user clears the part after
power-up, the output is actively driven to 0 V (if the channel
has been enabled for clear).
After device power on, or a device reset, it is recommended to
wait 100 μs or more before writing to the device to allow time
for internal calibrations to take place.
SERIAL INTERFACE
The AD5755 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI, MICROWIRE, and DSP standards. Data coding
is always straight binary.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If packet error checking, or PEC (see the Device Features
section), is enabled, an additional eight bits must be written to
the AD5755, creating a 32-bit serial interface.
There are two ways in which the DAC outputs can be updated:
individual updating or simultaneous updating of all DACs.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the DAC data register. The addressed DAC output is updated on
the rising edge of SYNC . See
information.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the DAC data register. Only the first write to each channel’s
DAC data register is valid after LDAC is brought high. Any subse-
quent writes while LDAC is still held high are ignored, though
Table 3
and
Figure 3
for timing
Rev. A | Page 30 of 52
they are loaded into the DAC data register. All the DAC outputs
are updated by taking LDAC low after SYNC is taken high.
TRANSFER FUNCTION
Table 6 shows the input code to ideal output voltage relationship
for the AD5755 for straight binary data coding of the ±10 V
output range.
Table 6. Ideal Output Voltage to Input Code Relationship
1111
1111
1000
0000
0000
Straight Binary Data Coding
MSB
Figure 73. Simplified Serial Interface of Input Loading Circuitry
V
REFIN
1111
1111
0000
0000
0000
LDAC
SYNC
SCLK
SDIN
Digital Input
1111
1111
0000
0000
0000
DAC INPUT
INTERFACE
REGISTER
DAC DATA
REGISTER
REGISTER
for One DAC Channel
16-BIT
LSB
DAC
LOGIC
DAC
1111
1110
0000
0001
0000
I/V AMPLIFIER
CALIBRATION
OUTPUT
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
AND GAIN
OFFSET
OUT
SDO
REF
REF
REF
REF
× (32,767/32,768)
× (32,766/32,768)
× (32,767/32,768)
Data Sheet
V
OUT_x