AD7880 Analog Devices, AD7880 Datasheet - Page 9

• Manufacturer Part Number: AD7880
• Description: CMOS, Single +5 V Supply, Low Power, 12-Bit Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7880

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 66kSPS
• Interface: Par
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip (Vref),Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC

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MICROPROCESSOR INTERFACING
The AD7880 high speed bus timing allows direct interfacing to
real time digital signal processors, DSPs, as well as modern high
speed, 16-bit microprocessors. Suitable microprocessor inter-
faces are shown in Figures 15 through 20.
AD7880–ADSP-2100 Interface
Figure 15 shows an interface between the AD7880 and the
ADSP-2100. Conversion is initiated using a timer to drive the
CONVST input asynchronously to the microprocessor. This al-
lows very accurate control of the sampling instant. When con-
version is complete, the AD7880 BUSY line goes high. An
inverter on this BUSY output drives the IRQ line low thus pro-
viding an interrupt to the ADSP-2100 when conversion is com-
pleted. The conversion result is then read from the AD7880 into
the ADSP-2100 with the following instruction:
where MR0 is the ADSP-2100 MR0 Register and
where
Figure 15. AD7880–ADSP-2100 (ADSP-2101/ADSP-2102)
Interface
AD7880-ADSP-2101/ADSP-2102 Interface
The interface outlined in Figure 15 also forms the basis for an
interface between the AD7880 and the ADSP-2101/ADSP-2102.
The READ line of the ADSP-2101/ADSP-2102 is labeled RD.
In this interface, the RD pulse width of the processor can be
programmed using the Data Memory Wait State Control Regis-
ter. The instruction used to read a conversion result is as out-
lined for the ADSP-2100.
AD7880-TMS32010 Interface
An interface between the AD7880 and the TMS32010 is shown
in Figure 16. Once again the conversion is initiated using an ex-
ternal timer and the TMS32010 is interrupted when conversion
is completed. The following instruction is used to read the con-
version result from the AD7880:
where D is Data Memory Address and
where
MR0 = DM(ADC)
IN D,ADC
ADC is the AD7880 address.
ADC is the AD7880 address.
(ADSP-2101/
ADSP-2102)
ADSP-2100
DMRD (RD)
DMD15
DMA13
DMA0
DMD0
IRQn
DMS
* ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
DATA BUS
EN
DECODE
ADDR
BUSY
CS
RD
DB11
DB0
AD7880*
CONVST
TIMER
–9–
AD7880–TMS320C25 Interface
Figure 17 shows an interface between the AD7880 and the
TMS320C25. As with the two previous interfaces, conversion is
initiated with a timer, and the processor is interrupted when the
conversion sequence is completed. The TMS320C25 does not
have a separate RD output to drive the AD7880 RD input di-
rectly. This has to be generated from the processor STRB and
R/W outputs with the addition of some logic gates. The RD sig-
nal is OR-gated with the MSC signal to provide the one WAIT
state required in the read cycle for correct interface timing.
Conversion results are read from the AD7880 using the follow-
ing instruction:
where D is Data Memory Address and
where
Some applications may require that the conversion be initiated
by the microprocessor rather than an external timer. One option
is to decode the AD7880 CONVST from the address bus so that
IN D,ADC
ADC is the AD7880 address.
Figure 17. AD7880–TMS320C25 Interface
TMS32010
Figure 16. AD7880–TMS32010 Interface
TMS320C25
READY
STRB
MSC
INTn
MEN
DEN
A15
R/W
D15
PA0
D15
PA2
INT
A0
D0
IS
D0
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
ADDRESS BUS
DATA BUS
EN
DECODE
DECODE
EN
ADDR
ADDR
DATA BUS
CONVST
CS
RD
BUSY
DB11
DB0
TIMER
DB11
DB0
CONVST
CS
BUSY
RD
AD7880*
TIMER
AD7880*
AD7880