AD7703 Analog Devices, AD7703 Datasheet - Page 8

• Manufacturer Part Number: AD7703
• Description: 20-Bit Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7703

• Resolution (bits): 20bit
• # Chan: 1
• Sample Rate: 16kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 2.5V,Uni 2.5V
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7703
DIGITAL FILTERING
The AD7703’s digital filter behaves like an analog filter, with a
few minor differences.
First, since digital filtering occurs after the analog-to-digital
conversion, it can remove noise injected during the conversion
process. Analog filtering cannot do this.
On the other hand, analog filtering can remove noise superim-
posed on the analog signal before it reaches the ADC. Digital
filtering cannot do this and noise peaks riding on signals near
full scale have the potential to saturate the analog modulator and
digital filter, even though the average value of the signal is within
limits. To alleviate this problem, the AD7703 has overrange
headroom built into the - modulator and digital filter that
allows overrange excursions of 100 mV. If noise signals are larger
than this, consideration should be given to analog input filtering,
or to reducing the gain in the input channel so that a full-scale
input (2.5 V) gives only a half-scale input to the AD7703 (1.25 V).
This will provide an overrange capability greater than 100% at
the expense of reducing the dynamic range by one bit (50%).
FILTER CHARACTERISTICS
The cutoff frequency of the digital filter is f
maximum clock frequency of 4.096 MHz, the cutoff frequency
of the filter is 10 Hz and the data update rate is 4 kHz.
Figure 9 shows the filter frequency response. This is a six-pole
Gaussian response that provides 55 dB of 60 Hz rejection for a
10 Hz cutoff frequency. If the clock frequency is halved to give a
5 Hz cutoff, 60 Hz rejection is better than 90 dB.
Since the AD7703 contains this low-pass filtering, there is a
settling time associated with step function inputs, and data will
be invalid after a step change until the settling time has elapsed.
The AD7703 is, therefore, unsuitable for high speed multiplex-
ing, where channels are switched and converted sequentially at
high rates, as switching between channels can cause a step change
in the input. However, slow multiplexing of the AD7703 is
possible, provided that the settling time is allowed to elapse
before data for the new channel is accessed.
Figure 9. Frequency Response of AD7703 Filter
–120
–160
–100
–140
–80
–20
–40
–60
20
0
1
FREQUENCY – Hz
f
CLK
= 2MHz
10
f
CLK
CLK
f
CLK
= 1MHz
/409600. At the
= 4MHz
100
–8–
The output settling of the AD7703 in response to a step input
change is shown in Figure 10. The Gaussian response has fast
settling with no overshoot, and the worst-case settling time to
±0.0007% is 125 ms with a 4.096 MHz master clock frequency.
USING THE AD7703
SYSTEM DESIGN CONSIDERATIONS
The AD7703 operates differently from successive approximation
ADCs or integrating ADCs. Since it samples the signal continu-
ously, like a tracking ADC, there is no need for a start convert
command. The 20-bit output register is updated at a 4 kHz rate,
and the output can be read at any time, either synchronously or
asynchronously.
CLOCKING
The AD7703 requires a master clock input, which may be an exter-
nal TTL/CMOS compatible clock signal applied to the CLKIN
pin (CLKOUT not used). Alternatively, a crystal of the correct
frequency can be connected between CLKIN and CLKOUT,
when the clock circuit will function as a crystal controlled oscillator.
Figure 11 shows a simple model of the on-chip gate oscillator
and Table II gives some typical capacitor values to be used with
various resonators.
100
80
60
40
20
0
0
Figure 11. On-Chip Gate Oscillator
Figure 10. AD7703 Step Response
g
m
= 1500 MHO
10pF
5M
R1
40
AD7703
10pF
TIME – ms
80
2
3
X1
*SEE TABLE II
C1*
120
C2*
160
REV. E