AD7703 Analog Devices, AD7703 Datasheet - Page 4

• Manufacturer Part Number: AD7703
• Description: 20-Bit Sigma-Delta ADC
• Manufacturer: Analog Devices

Specifications of AD7703

• Resolution (bits): 20bit
• # Chan: 1
• Sample Rate: 16kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Bip,SE-Uni
• Ain Range: Bip 2.5V,Uni 2.5V
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

TIMING CHARACTERISTICS
AD7703
Parameter
f
t
t
t
t
t
SSC MODE
SEC MODE
NOTES
10
11
Specifications subject to change without notice.
1
2
3
4
5
6
7
8
9
CLKIN
r
f
1
2
3
can draw higher current than specified and possibly become uncalibrated.
is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is
the true bus relinquish time of the part and as such is independent of external bus loading capacitance.
as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high
sooner than four CLKIN cycles plus 160 ns after CS goes low.
Sample tested at 25°C to ensure compliance. All input signals are specified with t
See Figures 1 to 6.
CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device
The AD7703 is production tested with f
Specified using 10% and 90% points on waveform of interest.
In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.
t
t
If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.
5
5
If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be
SDATA is clocked out on the falling edge of the SCLK input.
6
4
9
t
t
t
7
t
t
t
f
t
t
t
t
t
t
, t
and t
4
5
6
8
9
10
SCLK
11
12
13
14
15
16
7
8
10
7, 10
11
8, 9
8
8
, t
3, 4
13
15
, and t
are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
16
Figure 1. Load Circuit for Access Time
and Bus Relinquish Time
are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number
(A, B Versions)
Limit at T
200
5
200
5
50
50
0
50
1000
3/f
100
250
300
790
l/f
4/f
5
35
160
160
150
250
200
OUTPUT
CLKIN
CLKIN
CLKIN
PIN
TO
+ 200
100pF
+ 200
C
MIN
L
, T
CLKIN
MAX
at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.
I
1.6mA
I OH
200 A
OL
1, 2
150
Limit at T
(S, T Versions)
200
5
200
5
50
50
0
50
1000
3/f
100
250
300
790
l/f
4/f
5
35
160
160
250
200
CLKIN
CLKIN
CLKIN
+
(AV
f
2.1V
CLKIN
DD
+ 200
+ 200
= 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DV
= DV
MIN
DD
, T
= +5 V
MAX
kHz min
MHz max Typically 4.096 MHz
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns max
MHz max Serial Clock Input Frequency
ns min
ns min
ns max
ns max
ns max
ns max
Unit
–4–
r
= t
10%; AV
f
= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
SS
Master Clock Frequency: Internal Gate Oscillator
Master Clock Frequency: Externally Supplied
SC1, SC2 to CAL High Setup Time
SC1, SC2 Hold Time after CAL Goes High
SLEEP High to CLKIN High Setup Time
Data Access Time (CS Low to Data Valid)
SCLK Falling Edge to Data Valid Delay (25 ns typ)
MSB Data Setup Time. Typically 380 ns.
SCLK High Pulsewidth. Typically 240 ns.
SCLK Low Pulsewidth. Typically 730 ns.
SCLK Rising Edge to Hi-Z Delay (l/f
CS High to Hi-Z Delay
SCLK Input High Pulsewidth
SCLK Low Pulsewidth
Data Access Time (CS Low to Data Valid). Typically 80 ns.
SCLK Falling Edge to Data Valid Delay. Typically 75 ns.
CS High to Hi-Z Delay
SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.
Conditions/Comments
Digital Output Rise Time. Typically 20 ns.
Digital Output Fall Time. Typically 20 ns.
= DV
Figure 2. Calibration Control Timing
SC1, SC2
SS
SLEEP
CLKIN
= –5 V
CAL
Figure 3. Sleep Mode Timing
10%; AGND = DGND = O V;
SC1, SC2 VALID
t
1
DD
; unless otherwise noted.)
t
3
t
2
CLKIN
+ 100 ns typ)
REV. E