AD7713 Analog Devices, AD7713 Datasheet - Page 7

• Manufacturer Part Number: AD7713
• Description: CMOS, Low Power 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Current Sources
• Manufacturer: Analog Devices

Specifications of AD7713

• Resolution (bits): 24bit
• # Chan: 3
• Sample Rate: 3.9kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p,Uni (Vref) x 4,Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
REV. D
Mnemonic
SCLK
MCLK IN
MCLK OUT
A0
SYNC
MODE
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
STANDBY
AV
RTD1
REF IN(–)
REF IN(+)
DD
Function
Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the
device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK be-
comes active when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns
high or when the device has completed transmission of an output word. When MODE is low, the device
is in its external clocking mode and the SCLK pin acts as an input. This input serial clock can be a con-
tinuous clock with all data transmitted in a continuous train of pulses. Alternatively, it can be a
noncontinuous clock with the information being transmitted to the AD7713 in smaller batches of data.
Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A
crystal can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be
driven with a CMOS-compatible clock and MCLK OUT left unconnected. The clock input frequency is
nominally 2 MHz.
When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT.
Address Input. With this input low, reading and writing to the device is to the control register. With
this input high, access is to either the data register or the calibration registers.
Logic Input. Allows for synchronization of the digital filters when using a number of AD7713s. It
resets the nodes of the digital filter.
Logic Input. When this pin is high, the device is in its self-clocking mode. With this pin low, the
device is in its external clocking mode.
Analog Input Channel 1. Positive input of the programmable gain differential analog input. The
AIN1(+) input is connected to an output current source that can be used to check that an external
transducer has burnt out or gone open circuit. This output current source can be turned on/off via the
control register.
Analog Input Channel 1. Negative input of the programmable gain differential analog input.
Analog Input Channel 2. Positive input of the programmable gain differential analog input.
Analog Input Channel 2. Negative input of the programmable gain differential analog input.
Logic Input. Taking this pin low shuts down the internal analog and digital circuitry, reducing power
consumption to less than 100 µW.
Analog Positive Supply Voltage, 5 V to 10 V.
Constant Current Output. A nominal 200 µA constant current is provided at this pin, which can be
used as the excitation current for RTDs. This current can be turned on or off via the control register.
Reference Input. The REF IN(–) can lie anywhere between AV
greater than REF IN(–).
Reference Input. The reference input is differential providing that REF IN(+) is greater than REF
IN(–). REF IN(+) can lie anywhere between AV
PIN FUNCTION DESCRIPTION
MCLK OUT
PDIP, CERDIP, AND SOIC
STANDBY
MCLK IN
AIN1(+)
AIN1(–)
AIN2(+)
AIN2(–)
PIN CONFIGURATION
MODE
SYNC
SCLK
AV
A0
DD
10
11
12
1
2
3
4
5
6
7
8
9
(Not to Scale)
AD7713
TOP VIEW
–7–
19
18
16
24
23
22
21
20
17
15
14
13
DGND
DV
SDATA
DRDY
RFS
TFS
AGND
AIN3
RTD2
REF IN(+)
REF IN(–)
RTD1
DD
DD
and AGND.
DD
and AGND, provided REF IN(+) is
AD7713