AD7713 Analog Devices, AD7713 Datasheet - Page 12

• Manufacturer Part Number: AD7713
• Description: CMOS, Low Power 24-Bit Sigma-Delta, Signal Conditioning ADC with Matched RTD Current Sources
• Manufacturer: Analog Devices

Specifications of AD7713

• Resolution (bits): 24bit
• # Chan: 3
• Sample Rate: 3.9kSPS
• Interface: Ser
• Analog Input Type: Diff-Bip,Diff-Uni,SE-Uni
• Ain Range: (2Vref/PGA Gain) p-p,Uni (Vref) x 4,Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC

AD7713
Figures 2a and 2b gives similar information to that outlined in
Table I. In this plot, the output rms noise is shown for the full
range of available cutoff frequencies rather than for some typical
cutoff frequencies as in Tables I and II. The numbers given in
these plots are typical values at 25°C.
CIRCUIT DESCRIPTION
The AD7713 is a - ADC with on-chip digital filtering, intended
for the measurement of wide dynamic range, low frequency signals,
such as those in industrial control or process control applications. It
contains a - (or charge balancing) ADC, a calibration
microcontroller with on-chip static RAM, a clock oscillator, a
digital filter, and a bidirectional serial communications port.
The part contains three analog input channels, two program-
mable gain differential input channels, and one programmable
gain high-level single-ended input channel. The gain range on
both inputs is from 1 to 128. For the AIN1 and AIN2 inputs,
this means that the input can accept unipolar signals of between
0 mV to 20 mV and 0 V to 2.5 V or bipolar signals in the range
from ± 20 mV to ± 2.5 V when the reference input voltage equals
2.5 V. The input voltage range for the AIN3 input is 4
GAIN and is 0 V to 10 V with the nominal reference of 2.5 V and
a ANALOG gain of 1. The input signal to the selected analog
input channel is continuously sampled at a rate determined by
10000.0
Figure 2a. Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 1 to 8)
Figure 2b. Plot of Output Noise vs. Gain and Notch
Frequency (Gains of 16 to 128)
1000.0
1000.0
100.0
100.0
10.0
10.0
1.0
0.1
1.0
0.1
10
10
NOTCH FREQUENCY (Hz)
NOTCH FREQUENCY (Hz)
100
100
1k
1k
GAIN OF 1
GAIN OF 4
GAIN OF 2
GAIN OF 8
GAIN OF 16
GAIN OF 32
GAIN OF 64
GAIN OF 128
V
10k
10k
REF
/
–12–
the frequency of the master clock, MCLK IN, and the selected
gain (see Table III). A charge balancing ADC ( - modulator)
converts the sampled signal into a digital pulse train whose duty
cycle contains the digital information. The programmable gain
function on the analog input is also incorporated in this -
modulator with the input sampling frequency being modified to
give the higher gains. A sinc
output of the - modulator and updates the output register at
a rate determined by the first notch frequency of this filter. The
output data can be read from the serial port randomly or peri-
odically at any rate up to the output register update rate. The
first notch of this digital filter (and therefore its –3 dB frequency)
can be programmed via an on-chip control register. The
programmable range for this first notch frequency is from
1.952 Hz to 205.59 Hz, giving a programmable range for the
–3 dB frequency of 0.52 Hz to 53.9 Hz.
The basic connection diagram for the part is shown in Figure 3.
This shows the AD7713 in the external clocking mode with
both the AV
from the analog 5 V supply. Some applications will have sepa-
rate supplies for both AV
cases, the analog supply will exceed the 5 V digital supply (see the
Power Supplies and Grounding section).
The AD7713 provides a number of calibration options that can
be programmed via the on-chip control register. A calibration
cycle can be initiated at any time by writing to this control regis-
ter. The part can perform self-calibration using the on-chip
calibration microcontroller and SRAM to store calibration
parameters. Other system components may also be included in
the calibration loop to remove offset and gain errors in the input
channel using the system calibration mode. Another option is a
background calibration mode where the part continuously
performs self-calibration and updates the calibration coeffi-
cients. Once the part is in this mode, the user does not have to
worry about issuing periodic calibration commands to the device
or asking the device to recalibrate when there is a change in the
ambient temperature or power supply voltage.
ANALOG INPUT
ANALOG INPUT
SINGLE-ENDED
ANALOG INPUT
DIFFERENTIAL
DIFFERENTIAL
ANALOG 5V
GROUND
GROUND
ANALOG
DIGITAL
REFERENCE
SUPPLY
DD
Figure 3. Basic Connection Diagram
2.5V
DV
and DV
DD
10 F
AIN1(+)
AIN2(+)
AIN3
STANDBY
AGND
DGND
REF IN(+)
AIN1(–)
AIN2(–)
REF IN(–)
DD
DD
pins of the AD7713 being driven
0.1 F
3
and DV
AV
digital low-pass filter processes the
AD7713
DD
DV
DD
DD
MCLK OUT
, and in some of these
MCLK IN
SDATA
MODE
DRDY
SCLK
SYNC
RFS
TFS
A0
DATA
READY
TRANSMIT
(WRITE)
RECEIVE
(READ)
SERIAL
DATA
SERIAL
CLOCK
ADDRESS
INPUT
DV
REV. D
DD