AD7715 Analog Devices, AD7715 Datasheet - Page 6

• Manufacturer Part Number: AD7715
• Manufacturer: Analog Devices

Specifications of AD7715

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 19.2kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (Vref/PGA Gain) p-p,Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC,SOP

AD7715
Parameter
LOGIC OUTPUTS (Including MCLK OUT)
1
2
3
4
5
6
7
8
9
10
11
12
13
Temperature range as follows: A version, −40°C to +85°C.
A calibration is effectively a conversion, so these errors are of the order of the conversion noise shown in Table 15 to Table 22. This applies after calibration at the
temperature of interest.
Recalibration at any temperature removes these drift errors.
Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar and bipolar input ranges.
Full-scale drift includes zero-scale drift (unipolar offset drift or bipolar zero drift) and applies to both unipolar and bipolar input ranges.
Gain error does not include zero-scale errors. It is calculated as full-scale error–unipolar offset error for unipolar ranges and Full-Scale Error–Bipolar Zero Error for
bipolar ranges.
Gain error drift does not include unipolar offset drift/bipolar zero drift. It is effectively the drift of the part if zero scale calibrations only were performed.
These numbers are guaranteed by design and/or characterization.
This common-mode voltage range is allowed provided that the input voltage on AIN(+) or AIN(−) does not go more positive than AV
than AGND − 30 mV.
than AV
The analog input voltage range on AIN(+) is given here with respect to the voltage on AIN(−). The absolute voltage on the analog inputs should not go more positive
V
These logic output levels apply to the MCLK OUT only when it is loaded with one CMOS load.
Sample tested at 25°C to ensure compliance.
V
V
Floating State Leakage Current
Floating State Output Capacitance
Data Output Coding
REF
OL
OH
= REF IN(+) − REF IN(−).
, Output Low Voltage
, Output High Voltage
DD
+ 30 mV or go more negative than AGND − 30 mV.
1
13
Min
DV
DD
− 0.6
Typ
9
Binary
Offset binary
Rev. D | Page 6 of 40
Max
0.4
±10
Unit
V
V
μA
pF
Conditions/Comments
I
I
Unipolar mode
Bipolar mode
SINK
SOURCE
= 100 μA except for MCLK OUT
= 100 μA except for MCLK OUT
DD
+ 30 mV or go more negative
12
12