AD7715 Analog Devices, AD7715 Datasheet - Page 22

• Manufacturer Part Number: AD7715
• Manufacturer: Analog Devices

Specifications of AD7715

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 19.2kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: (Vref/PGA Gain) p-p,Uni (Vref)/(PGA Gain)
• Adc Architecture: Sigma-Delta
• Pkg Type: DIP,SOIC,SOP

AD7715
Filter Characteristics
The AD7715’s digital filter is a low-pass filter with a (sinx/x)
response (also called sinc
is described in the z-domain by
and in the frequency domain by
where N is the ratio of the modulator rate to the output rate and
f
Figure 6 shows the filter frequency response for a cutoff frequency
of 15.72 Hz which corresponds to a first filter notch frequency
of 60 Hz. The plot is shown from dc to 390 Hz. This response is
repeated at either side of the digital filter’s sample frequency
and at either side of multiples of the filter’s sample frequency.
The response of the filter is similar to that of an averaging filter
but with a sharper roll-off. The output rate for the digital filter
corresponds with the positioning of the first notch of the filter’s
frequency response. Thus, for the plot of Figure 6 where the
output rate is 60 Hz, the first notch of the filter is at 60 Hz. The
notches of this (sinx/x)
first notch. The filter provides attenuation of better than 100 dB
at these notches.
The cutoff frequency of the digital filter is determined by the
value loaded to the FS0 to FS1 bits in the setup register. program-
ming a different cutoff frequency via FS0 and FS1 does not alter
the profile of the filter response; it changes the frequency of the
notches. The output update of the part and the frequency of the
first notch correspond.
MOD
is the modulator rate.
H
H
–100
–120
–140
–160
–180
–200
–220
–240
(
–20
–40
–60
–80
(
z
f
0
)
)
0
=
=
⎡
⎢
⎢
⎣
Figure 6. Frequency Response of AD7715 Filter
N
1
N
1
×
×
60
1
1
Sin
−
−
Sin
z
z
⎛
⎜
⎜
⎝
3
−
N
−
120
filter are repeated at multiples of the
N
1
⎛
⎜
⎜
⎝
3
). The transfer function for this filter
π
×
⎤
⎥
⎥
⎦
×
3
FREQUENCY (Hz)
π
×
f
f
S
180
f
⎞
⎟
⎟
⎠
f
S
⎞
⎟
⎟
⎠
3
240
300
360
3
Rev. D | Page 22 of 40
Because the AD7715 contains this on-chip, low-pass filtering,
there is a settling time associated with step function inputs and
data on the output is invalid after a step change until the settling
time has elapsed. The settling time depends upon the output
rate chosen for the filter. The settling time of the filter to a full-
scale step input can be up 4 times the output data period. For a
synchronized step input (using the FSYNC function), the
settling time is 3 times the output data period.
Post-Filtering
The on-chip modulator provides samples at a 19.2 kHz output
rate with f
these samples to provide data at an output rate that corresponds
to the programmed output rate of the filter. Because the output
data rate is higher than the Nyquist criterion, the output rate
for a given bandwidth satisfys most application requirements.
However, there may be some applications that require a higher
data rate for a given bandwidth and noise performance.
Applications that need this higher data rate do require some
post-filtering following the digital filter of the AD7715.
For example, if the required bandwidth is 7.86 Hz but the
required update rate is 100 Hz, the data can be taken from the
AD7715 at the 100 Hz rate giving a −3 dB bandwidth of 26.2 Hz.
Post-filtering can be applied to this to reduce the bandwidth
and output noise, to the 7.86 Hz bandwidth level, while
maintaining an output rate of 100 Hz.
Post-filtering can also be used to reduce the output noise from
the device for bandwidths below 13.1 Hz. At a gain of 128 and
a bandwidth of 13.1 Hz, the output rms noise is 520 nV. This is
essentially device noise or white noise and because the input is
chopped, the noise has a primarily flat frequency response. By
reducing the bandwidth below 13.1 Hz, the noise in the resultant
pass-band can be reduced. A reduction in bandwidth by a factor
of 2 results in a reduction of approximately 1.25 in the output
rms noise. This additional filtering results in a longer settling time.
CLK IN
at 2.4576 MHz. The on-chip digital filter decimates