AD7854 Analog Devices, AD7854 Datasheet - Page 9

• Manufacturer Part Number: AD7854
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Parallel Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7854

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

REV. B
CONTROL REGISTER
The arrangement of the control register is shown below. The control register is a write only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register is described
below. The power-up status of all bits is 0.
Bit
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CALMD
0
0
0
0
1
1
1
1
Mnemonic
ZERO
ZERO
ZERO
ZERO
PMGT1
PMGT0
RDSLT1
RDSLT0
AMODE
CONVST
CALMD
CALSLT1
CALSLT0
STCAL
CALSLT1
0
0
1
1
0
0
1
1
RDSLT0
MSB
ZERO
CALSLT0
0
1
0
1
0
1
0
1
position selects range 0 to V
below AIN(–) and AIN(–) cannot go below AGND and data coding is straight binary. A logic 1 in this
bit position selects range –V
cannot go below AGND, so for this range, AIN(–) needs to be biased to at least +V
AIN(+) to go as low as AIN(–) –V
cally reset to 0 at the end of conversion. This bit may also used in conjunction with system calibration
(see Calibration section).
With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on the calibration registers for more details).
Comment
These four bits must be set to 0 when writing to the control register.
Power Management Bits. These two bits are used for putting the part into various power-down modes
(See Power-Down section for more details).
Theses two bits determine which register is addressed for the read operations. See Table II.
Analog Mode Bit. This pin allows two different analog input ranges to be selected. A logic 0 in this bit
Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-
Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).
Calibration Selection Bits and Start Calibration Bit. These bits have two functions.
With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per-
formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.
AMODE
ZERO
internal gain error and finally the internal offset error are removed. This is the default setting.
system gain error calibration, and finally the system offset error calibration.
Calibration Type
A full internal calibration is initiated. First the internal DAC is calibrated, then the
First the internal gain error is removed, then the internal offset error is removed.
The internal offset error only is calibrated out.
The internal gain error only is calibrated out.
A full system calibration is initiated. First the internal DAC is calibrated, followed by the
First the system gain error is calibrated out followed by the system offset error.
The system offset error only is removed.
The system gain error only is removed.
Control Register Bit Function Description
CONVST
ZERO
Table III. Calibration Selection
REF
REF
/2 to +V
CALMD
(i.e., AIN(+) – AIN(–) = 0 to V
ZERO
REF
–9–
/2 V. Data coding is twos complement for this range.
REF
/2 (i.e., AIN(+) – AIN(–) = –V
CALSLT1
PMGT1
CALSLT0
PMGT0
REF
). In this range AIN(+) cannot go
AD7854/AD7854L
REF
RDSLT1
STCAL
/2 to +V
LSB
REF
REF
/2 to allow
/2). AIN(+)