AD7854 Analog Devices, AD7854 Datasheet - Page 13

• Manufacturer Part Number: AD7854
• Description: 3 V to 5 V Single Supply, 200 kSPS, 12-Bit, Parallel Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7854

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 200kSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: DIP,SOIC,SOP

REV. B
CIRCUIT INFORMATION
The AD7854/AD7854L is a fast, 12-bit single supply A/D con-
verter. The part requires an external 4 MHz/1.8 MHz master
clock (CLKIN), two C
conversion and power supply decoupling capacitors. The part
provides the user with track/hold, on-chip reference, calibration
features, A/D converter and parallel interface logic functions on
a single chip. The A/D converter section of the AD7854/
AD7854L consists of a conventional successive-approximation
converter based around a capacitor DAC. The AD7854/
AD7854L accepts an analog input range of 0 to +V
can be tied to V
via a 150 kΩ resistor to the internal 2.5 V reference and to the
on-chip buffer.
A major advantage of the AD7854/AD7854L is that a conver-
sion can be initiated in software as well as applying a signal to
the CONVST pin. The part is available in a 28-Lead SSOP
package, and this offers the user considerable space saving advan-
tages over alternative solutions. The AD7854L version typically
consumes only 5.5 mW making it ideal for battery-powered
applications.
CONVERTER DETAILS
The master clock for the part is applied to the CLKIN pin.
Conversion is initiated on the AD7854/AD7854L by pulsing the
CONVST input or by writing to the control register and setting
the CONVST bit to 1. On the rising edge of CONVST (or at the
end of the control register write operation), the on-chip track/
hold goes from track to hold mode. The falling edge of the CLKIN
signal which follows the rising edge of CONVST initates the
conversion, provided the rising edge of CONVST (or WR when
converting via the control register) occurs typically at least 10 ns
before this CLKIN edge. The conversion takes 16.5 CLKIN
periods from this CLKIN falling edge. If the 10 ns setup time is
not met, the conversion takes 17.5 CLKIN periods.
The time required by the AD7854/AD7854L to acquire a signal
depends upon the source resistance connected to the AIN(+)
input. Please refer to the Acquisition Time section for more
details.
When a conversion is completed, the BUSY output goes low,
and the result of the conversion can be read by accessing the
data through the data bus. To obtain optimum performance
from the part, read or write operations should not occur during
the conversion or less than 200 ns prior to the next CONVST
rising edge. Reading/writing during conversion typically de-
grades the Signal to (Noise + Distortion) by less than 0.5 dBs.
The AD7854 can operate at throughput rates of over 200 kSPS
(up to 100 kSPS for the AD7854L).
With the AD7854L, 100 kSPS throughput can be obtained as
follows: the CLKIN and CONVST signals are arranged to give
a conversion time of 16.5 CLKIN periods as described above
and 1.5 CLKIN periods are allowed for the acquisition time.
With a 1.8 MHz clock, this gives a full cycle time of 10 µs,
which equates to a throughput rate of 100 kSPS.
DD
. The reference input to the part connected
REF
capacitors, a CONVST signal to start
REF.
V
REF
–13–
When using the software conversion start for maximum
throughput, the user must ensure the control register write
operation extends beyond the falling edge of BUSY. The falling
edge of BUSY resets the CONVST bit to 0 and allows it to be
reprogrammed to 1 to start the next conversion.
TYPICAL CONNECTION DIAGRAM
Figure 8 shows a typical connection diagram for the AD7854/
AD7854L. The AGND and the DGND pins are connected
together at the device for good noise suppression. The first
CONVST applied after power-up starts a self-calibration
sequence. This is explained in the calibration section of the data
sheet. Applying the RD and CS signals causes the conversion
result to be output on the 12 data pins. Note that after power is
applied to AV
the part requires (70 ms + 1/sample rate) for the internal refer-
ence to settle and for the self-calibration to be completed.
For applications where power consumption is a major concern,
the power-down options can be programmed by writing to the
part. See Power-Down section for more detail on low power
applications.
+3V TO +5V
0V TO 2.5V
ANALOG
SUPPLY
INPUT
REFERENCE
EXTERNAL
OPTIONAL
0.01 F
0.1 F
DD
10 F
and DV
Figure 8. Typical Circuit
REF192
AD780/
AIN(+)
AIN(–)
C
C
AGND
DGND
0.1 F
REF1
REF2
DD
AV
, and the CONVST signal is applied,
REF
AD7854L
AD7854/
DD
IN
DV
/REF
AD7854/AD7854L
DD
0.1nF EXTERNAL REFERENCE
0.1 F ON-CHIP REFERENCE
OUT
CONVST
CLKIN
HBEN
BUSY
0.1 F
DB11
DB0
WR
RD
CS
OSCILLATOR
4MHz/1.8MHz
START SIGNAL
CONVERSION
C/ P