AD9243 Analog Devices, AD9243 Datasheet - Page 18

• Manufacturer Part Number: AD9243
• Description: Complete 14-Bit, 3 MSPS Monolithic A/D Converter
• Manufacturer: Analog Devices

Specifications of AD9243

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,2 V p-p,5V p-p,Uni (Vref) x 2,Uni 2.0V,Uni 5.0V
• Adc Architecture: Pipelined
• Pkg Type: QFP

AD9243
until the analog input returns within the input range and an-
other conversion is completed. By logical ANDing OTR with
the MSB and its complement, overrange high or underrange low
conditions can be detected. Table V is a truth table for the over/
underrange circuit in Figure 43 which uses NAND gates. Sys-
tems requiring programmable gain conditioning of the AD9243
input signal can immediately detect an out-of-range condition,
thus eliminating gain selection iterations. Also, OTR can be
used for digital offset and gain calibration.
OTR
0
0
1
1
Digital Output Driver Considerations (DRVDD)
The AD9243 output drivers can be configured to interface with
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V
respectively. The AD9243 output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause glitches on the
supplies and may affect SINAD performance. Applications requir-
ing the AD9243 to drive large capacitive loads or large fanout
may require additional decoupling capacitors on DRVDD. In
extreme cases, external buffers or latches may be required.
Clock Input and Considerations
The AD9243 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. The clock
input must meet or exceed the minimum specified pulsewidth
high and low (t
defined in the Switching Specifications at the beginning of the
data sheet to meet the rated performance specifications. For
example, the clock input to the AD9243 operating at 3 MSPS
may have a duty cycle between 45% to 55% to meet this timing
requirement since the minimum specified t
MSB
MSB
Figure 43. Overrange or Underrange Logic
OTR
Table V. Out-of-Range Truth Table
CH
0
1
0
1
MSB
and t
CL
) specifications for the given A/D as
Analog Input Is
In Range
In Range
Underrange
Overrange
CH
and t
OVER = “1”
UNDER = “1”
CL
is 150 ns.
–18–
For clock rates below 3 MSPS, the duty cycle may deviate from
this range to the extent that both t
All high speed high resolution A/Ds are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
calculated with the following equation:
In the equation, the rms aperture jitter, t
sum square of all the jitter sources which include the clock in-
put, analog input signal, and A/D aperture jitter specification.
For example, if a 1.5 MHz full-scale sine wave is sampled by an
A/D with a total rms jitter of 15 ps, the SNR performance of the
A/D will be limited to 77 dB. Undersampling applications are
particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9243. As such, supplies for clock drivers should be separated
from the A/D output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other method),
it should be retimed by the original clock at the last step.
Most of the power dissipated by the AD9243 is from the analog
power supply. However, lower clock speeds will reduce digital
current slightly. Figure 44 shows the relationship between power
and clock rate.
Figure 44. AD9243 Power Consumption vs. Clock
Frequency
125
120
115
110
105
100
95
90
0
IN
1
SNR = 20 log
) due to only aperture jitter (t
CLOCK FREQUENCY – MHz
2
5V p-p
10
3
CH
[1/(2
2V p-p
and t
A
4
, represents the root-
CL
f
IN
are satisfied.
t
A
)]
5
A
) can be
6
REV. A