AD7729 Analog Devices, AD7729 Datasheet - Page 9

• Manufacturer Part Number: AD7729
• Description: 3 V, Dual Sigma-Delta ADC with Auxiliary DAC
• Manufacturer: Analog Devices

Specifications of AD7729

• Resolution (bits): 15bit
• # Chan: 2
• Sample Rate: 13MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOIC,SOP

REV. 0
FUNCTIONAL DESCRIPTION
BASEBAND CODEC
Receive Section
The receive section consists of I and Q receive channels, each
comprising of a simple switched-capacitor filter followed by a
15-bit sigma-delta ADC. On-board digital filters, which form
part of the sigma-delta ADCs, also perform critical system-level
filtering. Their amplitude and phase response characteristics
provide excellent adjacent channel rejection. The receive sec-
tion is also provided with a low power sleep mode to place the
receive section on standby between receive bursts, drawing only
minimal current.
Switched Capacitor Input
The receive section analog front-end is sampled at 13 MHz by a
switched-capacitor filter. The filter has a zero at 6.5 MHz as
shown in Figure 8a. The receive channel also contains a digital
low-pass filter (further details are contained in the following
section) which operates at a clock frequency of 6.5 MHz. Due
to the sampling nature of the digital filter, the passband is re-
peated about the operating clock frequency and at multiples of
the clock frequency (Figure 8b). Because the first null of the
switched-capacitor filter coincides with the first image of the
digital filter, this image is attenuated by an additional 30 dBs
(Figure 8c), further simplifying the external antialiasing require-
ments (see Figures 9 and 10).
The circuitry of Figure 9 implements first-order low-pass filters
with a 3 dB point at 338 kHz; these are the only filters that
must be implemented external to the baseband section to pre-
vent aliasing of the sampled signal.
DIGITAL FILTER
ANALOG FILTER
SYSTEM FILTER
FRONT-END
TRANSFER
TRANSFER
FUNCTION
TRANSFER
FUNCTION
FUNCTION
0 dBs
0 dBs
0 dBs
a) Switched-Cap Filter Frequency Response
b) Digital Filter Frequency Response
c) Overall System Response of the Receive
Channel
6.5
6.5
6.5
Figure 8.
13
13
13
19.5
19.5
19.5
MHz
MHz
MHz
–9–
Figure 10 shows the recommended single-ended analog input
circuit.
TO INPUT BIAS
QRx
V
IRx
Figure 10. Example Circuit for Single-Ended Input
BIAS
QRx
IRx
CIRCUITRY
HIGH SPEED
Figure 9. Example Circuit for Differential Input
BUFFER
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
100pF
0.1 F
100pF
100pF
100pF
0.1 F
0.1 F
0.1 F
100pF
100pF
REFCAP
IRxP
IRxN
QRxP
QRxN
REFCAP
REFOUT
IRxP
IRxN
QRxP
QRxN
REFOUT
AD7729
Q CHANNEL
AD7729
I CHANNEL
Q CHANNEL
I CHANNEL
REFERENCE
REFERENCE
VOLTAGE
VOLTAGE
AD7729