AD7675 Analog Devices, AD7675 Datasheet - Page 4

• Manufacturer Part Number: AD7675
• Manufacturer: Analog Devices

Specifications of AD7675

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: QFP

ABSOLUTE MAXIMUM RATINGS
Analog Inputs
Ground Voltage Differences
Supply Voltages
Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
Internal Power Dissipation
Internal Power Dissipation
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150° C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range
NOTES
1
2
3
4
AD7675
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7675 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings may cause perma-
See Analog Input section.
Specification is for device in free air: 48-Lead LQFP:
Specification is for device in free air: LFCSP:
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ± 7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
IN+
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . . ± 0.3 V
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
. . . . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
2
, IN–
2
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Typical
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
Busy High Width Maximum
Model
AD7675AST
AD7675ASTRL
AD7675ACP
AD7675ACPRL
EVAL-AD7675CB
EVAL-CONTROL BRD2
NOTES
1
2
, REF, REFGND . . . . . . . . . . . . . . . . . . . . . . . .
This board can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
demonstration purposes.
3
4
. . . . . . . . . . . . . . . . . . . . 700 mW
. . . . . . . . . . . . . . . . . . . . . . 2.5 W
1
Table I. Serial Clock Timings in Master Read after Convert
JA
1
= 26°C/W
2
JA
= 91°C/W,
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
JC
= 30°C/W.
ORDERING GUIDE
t
t
t
t
t
t
t
t
t
–4–
18
19
19
20
21
22
23
24
28
Figure 1. Load Circuit for Digital Interface Timing, SDOUT,
SYNC, SCLK Outputs, C
Package Description
Quad Flatpack (LQFP)
Quad Flatpack (LQFP)
Chip Scale (LFCSP)
Chip Scale (LFCSP)
Evaluation Board
Controller Board
0
0
3
25
40
12
7
4
2
3
2
Figure 2. Voltage Reference Levels for Timing
TO OUTPUT
NOTE
1
t
IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
DELAY
L
0.8V
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
0
1
17
50
70
22
21
18
4
60
2.5
PIN
60pF
C
L
1
1
0
17
100
140
50
49
18
30
140
3.5
2V
0.8V
500 A
1.6mA
L
= 10 pF
1
1
17
200
280
100
99
18
89
300
5.75
Package
Option
ST-48
ST-48
CP-48
CP-48
I
I
OL
OH
WARNING!
2V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
µs
1.4V
t
ESD SENSITIVE DEVICE
DELAY
2V
0.8V
REV. A