AD7675 Analog Devices, AD7675 Datasheet
AD7675
Specifications of AD7675
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AD7675 Summary of contents
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... Excellent INL The AD7675 has a maximum integral nonlinearity of 1.5 LSB with no missing 16-bit code. 2. Superior AC Performances The AD7675 has a minimum dynamic typical. 3. Fast Throughput The AD7675 is a 100 kSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. 4. Single-Supply Operation The AD7675 operates from a single 5 V supply and typically dissipates only 17 mW ...
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... AD7675–SPECIFICATIONS Parameter Conditions RESOLUTION ANALOG INPUT Voltage Range V Operating Input Voltage V Analog Input CMRR f Input Current 100 kSPS Throughput Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Transition Noise 2 +Full-Scale Error 2 –Full-Scale Error 2 Zero Error AVDD = 5 V ± ...
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... See Table I 1. pF; otherwise, the load maximum. L AD7675 Unit ns µs ns µ µs µs ns µ µs µ ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7675 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... OGND P Input/Output Interface Digital Power Ground 18 OVDD P Input/Output Interface Digital Power. Nominally at the same supply than the supply of the host interface ( V). 19 DVDD P Digital Power. Nominally DGND P Digital Power Ground REV. A PIN FUNCTION DESCRIPTIONS –5– AD7675 ...
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... Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled also used to gate the external serial clock. Reset Input. When set to a logic HIGH, reset the AD7675. Current conversion if any is aborted. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver- sions are inhibited after the current one is completed ...
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... Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. TRANSIENT RESPONSE The time required for the AD7675 to achieve its rated accuracy after a full-scale step function is applied to its input. –7– AD7675 ...
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... AD7675 –Typical Performance Characteristics 1.00 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 0 16384 32768 CODE TPC 1. Integral Nonlinearity vs. Code 9000 8246 8118 8000 7000 6000 5000 4000 3000 2000 1000 0000 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 CODE IN HEXA TPC 2. Histogram of 16,384 Conversions Input at ...
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... TPC 12. Power-Down Operating Currents vs. Temperature –9– AD7675 OVDD = 2. OVDD = 2. OVDD = 5. OVDD = 5. 100 150 C – AVDD DVDD OVDD 100 1k 10k SAMPLING RATE – SPS ...
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... ADC that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. The AD7675 can be operated from a single 5 V supply and be interfaced to either digital logic housed in a 48-lead LQFP package that combines space savings and allows flexible configurations as either serial or parallel interface ...
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... Figure 5. Typical Connection Diagram. ( ± 2.5 V Range Shown) TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7675. Different circuitry shown on this diagram is optional and is discussed below. Analog Inputs Figure 6 shows a simplified analog input section of the AD7675. AVDD IN+ IN– AGND Figure 6. Simplified Analog Input The diodes shown in Figure 6 provide ESD protection for the inputs ...
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... S SNR where f is the –3 dB input bandwidth of the AD7675 (3.9 MHz) – the cutoff frequency of the input filter if any is used the noise factor of the amplifier ( buffer con- figuration the equivalent input noise voltage of the op amp in ...
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... During the acquisition phase, the operating currents are very low, which allows a significant power saving when the conversion rate is reduced as shown in Figure 10. This feature makes the AD7675 ideal for very low power battery applications. It should be noted that the digital interface remains active even during the acquisition phase ...
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... CNVST Figure 12. RESET Timing For other applications, conversions can be automatically initi- ated. If CNVST is held low when BUSY is low, the AD7675 controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the AD7675 keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low ...
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... SCLK pin. MASTER SERIAL INTERFACE Internal Clock The AD7675 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7675 also generates a SYNC signal to indicate to the host when the CS ...
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... MHz, which accommodates both slow digital host inter- face and the fastest serial reading. Finally, in this mode only, the AD7675 provides a “daisy chain” feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing compo- nent count and wiring connections when it is desired as it is, for instance, in isolated multiconverters applications ...
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... SPI-equipped microcontroller like the MC68HC11. To accommodate the slower speed of the microcontroller, the AD7675 acts as a slave device and data must be read after con- version. This mode also allows the “daisy chain” feature. The convert command could be initiated in response to an internal timer interrupt ...
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... This will reduce the effect of feedthrough through the board. The power supply lines to the AD7675 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’ ...
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... Body (CP-48) Dimensions shown in millimeters 7.00 0.60 MAX 0.60 MAX 37 36 6.75 TOP BSC SQ VIEW 0.50 0. 0.30 0.70 MAX 0.65 NOM COPLANARITY 0.05 MAX 0.02 NOM 0.50 BSC COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 –19– AD7675 9.00 BSC 7.00 TOP VIEW BSC (PINS DOWN 0.27 0.22 0.17 0.30 0.23 PIN 1 0.18 INDICATOR 48 1 5.25 BOTTOM 4.70 VIEW 2 ...
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Revision History Location 7/02—Data Sheet changed from REV REV. A. Added 48-Lead LFCSP to FEATURES and GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . ...