AD7484 Analog Devices, AD7484 Datasheet - Page 7

• Manufacturer Part Number: AD7484
• Description: 14-Bit, 3 MSPS SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7484

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: QFP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1, 5, 13, 46
2
3, 4, 6, 11, 12,
14, 15, 47, 48
7
8
9
10
16
17
18
19
20
21
22 to 28, 33 to
39
29
30, 31
32
Mnemonic
AV
C
AGND
VIN
REFOUT
REFIN
REFSEL
STBY
NAP
CS
RD
WRITE
BUSY
D0 to D13
DV
DGND
V
DRIVE
BIAS
DD
DD
Description
Positive Power Supply for Analog Circuitry.
Decoupling Pin for Internal Bias Voltage. A 1 nF capacitor should be placed between this pin and AGND.
Power Supply Ground for Analog Circuitry.
Analog Input. Single ended analog input channel.
Reference Output. REFOUT connects to the output of the internal 2.5 V reference buffer. A 470 nF capacitor
must be placed between this pin and AGND.
Reference Input. A 470 nF capacitor must be placed between this pin and AGND. When using an external
voltage reference source, the reference voltage should be applied to this pin.
Reference Decoupling Pin. When using the internal reference, a 1 nF capacitor must be connected from this
pin to AGND. When using an external reference source, this pin should be connected directly to AGND.
Standby Logic Input. When this pin is logic high, the device is placed in standby mode. See the Power Saving
section for further details.
Nap Logic Input. When this pin is logic high, the device is placed in a very low power mode. See the Power
Saving section for further details.
Chip Select Logic Input. This pin is used in conjunction with RD to access the conversion result. The data bus
is brought out of three-state and the current contents of the output register driven onto the data lines
following the falling edge of both CS and RD. CS is also used in conjunction with WRITE to perform a write to
the offset register. CS can be hardwired permanently low.
Read Logic Input. Used in conjunction with CS to access the conversion result.
Write Logic Input. Used in conjunction with CS to write data to the offset register. When the desired offset
word has been placed on the data bus, the WRITE line should be pulsed high. It is the falling edge of this
pulse that latches the word into the offset register.
Busy Logic Output. This pin indicates the status of the conversion process. The BUSY signal goes low after
the falling edge of CONVST and stays low for the duration of the conversion. In Parallel Mode 1, the BUSY
signal returns high when the conversion result has been latched into the output register. In Parallel Mode 2,
the BUSY signal returns high as soon as the conversion has been completed, but the conversion result does
not get latched into the output register until the falling edge of the next CONVST pulse.
Data I/O Bits. D13 is MSB. These are three-state pins that are controlled by CS, RD, and WRITE. The operating
voltage level for these pins is determined by the V
Positive Power Supply for Digital Circuitry.
Ground Reference for Digital Circuitry.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface logic of
the device operates.
REFOUT
REFSEL
AGND
AGND
AGND
REFIN
AGND
AGND
C
AV
AV
BIAS
VIN
DD
DD
10
11
12
1
2
3
4
5
6
7
8
9
48 47 46 45 44
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
IDENTIFIER
Figure 2. Pin Configuration
Rev. C | Page 7 of 20
(Not to Scale)
AD7484
TOP VIEW
43 42 41 40
39 38 37
DRIVE
input.
36
35
34
33
32
31
30
29
28
26
25
27
D10
D9
D8
D7
V
DGND
DGND
DV
D6
D5
D4
D3
DRIVE
DD
AD7484