AD7484 Analog Devices, AD7484 Datasheet - Page 12

• Manufacturer Part Number: AD7484
• Description: 14-Bit, 3 MSPS SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7484

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 3MSPS
• Interface: Par
• Analog Input Type: SE-Uni
• Ain Range: Uni 2.5V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7484
CIRCUIT DESCRIPTION
CONVERTER OPERATION
The AD7484 is a 14-bit algorithmic successive approximation
ADC based around a capacitive DAC. It provides the user with
track-and-hold, reference, an ADC, and versatile interface logic
functions on a single chip. The normal analog input signal range
that the AD7484 can convert is 0 V to 2.5 V. By using the offset
and overrange features on the ADC, the AD7484 can convert
analog input signals from −200 mV to +2.7 V while operating
from a single 5 V supply. The part requires a 2.5 V reference,
which can be provided from the internal reference or an external
reference source. Figure 11 shows a simplified schematic of the
ADC. The control logic, SAR, and capacitive DAC are used to
add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back to a balanced condition.
Conversion is initiated on the AD7484 by pulsing the CONVST
input. On the falling edge of
from track mode to hold mode and the conversion sequence is
started. Conversion time for the part is 300 ns.
the ADC during conversion. When conversion starts, SW2
opens and SW1 moves to Position B, causing the comparator to
become unbalanced. The ADC then runs through its successive-
approximation routine and brings the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion result is available in the SAR register.
AGND
VIN
SW1
A
Figure 11. Simplified Block Diagram of the AD7484
CONTROL
INPUTS
B
V
VIN
REF
Figure 12. ADC Conversion Phase
CAPACITIVE
SWITCHES
CONTROL
LOGIC
SAR
DAC
SW2
CONVST , the track-and-hold goes
14-BIT PARALLEL
OUTPUT DATA
COMPARATOR
COMPARATOR
+
–
Figure 12
CONTROL LOGIC
CAPACITIVE
shows
DAC
Rev. C | Page 12 of 20
At the end of conversion, the track-and-hold returns to track
mode and the acquisition time begins. The track-and-hold
acquisition time is 70 ns. Figure 13 shows the ADC during its
acquisition phase. SW2 is closed and SW1 is in Position A. The
comparator is held in a balanced condition, and the sampling
capacitor acquires the signal on V
AGND
ANALOG INPUT
Figure 14 shows the analog input circuit used to obtain the data
for the fast fourier transfer (FFT) plot shown in Figure 3. The
circuit uses the
analog signal is applied and biased up with a stable, low noise dc
voltage connected to the labeled terminal, as shown in Figure 11. A
220 pF compensation capacitor is connected between Pin 5 of
the AD829 and the analog ground plane. The AD829 is supplied
with +12 V and −12 V supplies. The supply pins are decoupled
as close to the device as possible with both a 0.1 µF and a 10 µF
capacitor connected to each pin. In each case, the 0.1 µF capacitor
should be the closer of the two caps to the device. More informa-
tion on the AD829 is available at www.analog.com.
VIN
VOLTAGE
Figure 14. Analog Input Circuit Used for 10 kHz Input Tone
Figure 15. Analog Input Circuit Used for 1 MHz Input Tone
SW1
SIGNAL
VOLTAGE
A
BIAS
SIGNAL
AC
BIAS
B
AC
AD829
1kΩ
1kΩ
Figure 13. ADC Acquisition Phase
220Ω
50Ω
op amp as the input buffer. A bipolar
100Ω
2
3
SW2
+
–
150Ω
1
3
2
AD8021
8
+
–
220Ω
10pF
AD829
1
5
8
IN
+V
10pF
7
.
S
+V
COMPARATOR
5
–V
7
4
S
+
–
220pF
S
–V
4
S
6
6
VIN
CONTROL LOGIC
VIN
CAPACITIVE
DAC