AD7928 Analog Devices, AD7928 Datasheet - Page 23

• Manufacturer Part Number: AD7928
• Description: 8-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7928

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

POWER VS. THROUGHPUT RATE
By operating in auto shutdown mode on the AD7908/AD7918/
AD7928, the average power consumption of the ADC decreases
at lower throughput rates. Figure 25 shows how as the
throughput rate is reduced, the part remains in its shutdown
state longer and the average power consumption over time
drops accordingly.
For example, if the AD7928 is operated in a continuous
sampling mode with a throughput rate of 100 kSPS and an
SCLK of 20 MHz (AV
shutdown mode, that is, if PM1 = 0 and PM0 = 1, then the
power consumption is calculated as follows:
The maximum power dissipation during normal operation is
13.5 mW (AV
shutdown is one dummy cycle, that is, 1 μs, and the remaining
conversion time is another cycle, that is, 1 μs, then the AD7928
can be said to dissipate 13.5 mW for 2 μs during each
conversion cycle. For the remainder of the conversion cycle,
8 μs, the part remains in auto shutdown mode. The AD7928 can
be said to dissipate 2.5 μW for the remaining 8 μs of the
conversion cycle. If the throughput rate is 100 kSPS, the cycle
time is 10 μs and the average power dissipated during each cycle is
(2/10) × (13.5 mW) + (8 / 10) × (2.5 μW) = 2.702 mW
Figure 25 shows the maximum power vs. throughput rate when
using the auto shutdown mode with 3 V and 5 V supplies.
DOUT
SCLK
DIN
CS
KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS
1
DD
= 5 V). If the power-up time from auto
DUMMY CONVERSION
DD
INVALID DATA
= 5 V), and the device is placed in auto
Figure 24. Placing AD7928 into the Required Operating Mode After Supplies are Applied
12
16
1
Rev. D | Page 23 of 32
DUMMY CONVERSION
INVALID DATA
SERIAL INTERFACE
Figure 26, Figure 27, and Figure 28 show the detailed timing
diagrams for serial interfacing to the AD7908, AD7918, and
AD7928, respectively. The serial clock provides the conversion
clock and also controls the transfer of information to and from
the AD7908/AD7918/AD7928 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state; the analog input is sampled at
this point. The conversion is also initiated at this point and
requires 16 SCLK cycles to complete. The track-and-hold goes
back into track on the 14th SCLK falling edge as shown in
Figure 26 Figure 27
write is to the SHADOW register, in which case the track-and-
hold does not return to track until the rising edge of
Point C in
line goes back into three-state. If the rising edge of
before 16 SCLKs have elapsed, the conversion is terminated, the
DOUT line goes back into three-state, and the control register is
not updated; otherwise DOUT returns to three-state on the
16th SCLK falling edge as shown in
Figure 28
conversion process and to access data from the AD7908/
AD7918/AD7928. For the AD7908/AD7918/AD7928, the
12
0.01
0.1
10
1
0
,
. Sixteen serial clock cycles are required to perform the
16
AV
Figure 29
DD
Figure 25. AD7928 Power vs. Throughput Rate
= 5V
50
, and
. On the 16th SCLK falling edge, the DOUT
CONTROL REGISTER IS LOADED ON THE FIRST
12 CLOCK EDGES
1
100
DATA IN TO CONTROL REGISTER
AD7908/AD7918/AD7928
THROUGHPUT (kSPS)
Figure 28
150
INVALID DATA
200
at Point B, except when the
Figure 26 Figure 27
NEXT CONVERSION, USER CAN
CORRECT VALUE IN CONTROL
WRITE TO SHADOW REGISTER
REGISTER, VALID DATA FROM
AV
250
DD
12
IN NEXT CONVERSION
= 3V
,
300
16
CS occurs
CS , that is,
350
, and