AD7928 Analog Devices, AD7928 Datasheet - Page 15

• Manufacturer Part Number: AD7928
• Description: 8-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7928

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

CONTROL REGISTER
The control register on the AD7908/AD7918/AD7928 is a 12-bit, write-only register. Data is loaded from the DIN pin of the
AD7908/AD7918/AD7928 on the falling edge of SCLK. The data is transferred on the DIN line at the same time that the conversion
result is read from the part. The data transferred on the DIN line corresponds to the AD7908/AD7918/AD7928 configuration for the next
conversion. This requires 16 serial clocks for every data transfer. Only the information provided on the first 12 falling clock edges (after
CS falling edge) is loaded to the control register. MSB denotes the first bit in the data stream. The bit functions are outlined in
MSB
Table 7. Control Register Bit Functions
Bit
11
10
9
8 to 6
5, 4
3
2
1
0
Table 8. Channel Selection
ADD2
0
0
0
0
1
1
1
1
WRITE
Mnemonic
WRITE
SEQ
DON’TCARE
ADD2 to
ADD0
PM1, PM0
SHADOW
DON’TCARE
RANGE
CODING
SEQ
DON’TCARE
Comment
The value written to this bit of the control register determines whether or not the following 11 bits are loaded to the
control register. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the remaining 11 bits
are not loaded to the control register, and it remains unchanged.
The SEQ bit in the control register is used in conjunction with the SHADOW bit to control the use of the sequencer
function and access the SHADOW register (see the SHADOW register bit map).
These three address bits are loaded at the end of the present conversion sequence and select which analog input
channel is to be converted in the next serial transfer, or they can select the final channel in a consecutive sequence as
described in Table 10. The selected input channel is decoded as shown in Table 8. The address bits corresponding to
the conversion result are also output on DOUT prior to the 12 bits of data, see the Serial Interface section. The next
channel to be converted on is selected by the mux on the 14th SCLK falling edge.
Power Management Bits. These two bits decode the mode of operation of the AD7908/AD7918/AD7928 as shown in
Table 9.
The SHADOW bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer
function and access the SHADOW register (see Table 10).
This bit selects the analog input range to be used on the AD7908/AD7918/AD7928. If it is set to 0, the analog input
range extends from 0 V to 2 × REF
conversion). For 0 V to 2 × REF
This bit selects the type of output coding the AD7908/AD7918/AD7928 uses for the conversion result. If this bit is set to
0, the output coding for the part is twos complement. If this bit is set to 1, the output coding from the part is straight
binary (for the next conversion).
ADD1
0
0
1
1
0
0
1
1
ADD2
ADD1
ADD0
0
1
0
1
0
1
0
1
IN
, AV
IN
ADD0
. If it is set to 1, the analog input range extends from 0 V to REF
DD
Rev. D | Page 15 of 32
= 4.75 V to 5.25 V.
PM1
Analog Input Channel
V
V
V
V
V
V
V
V
IN
IN
IN
IN
IN
IN
IN
IN
0
1
2
3
4
5
6
7
PM0
SHADOW
AD7908/AD7918/AD7928
DON’TCARE
RANGE
IN
(for the next
Table 7
CODING
.
LSB