AD7927 Analog Devices, AD7927 Datasheet - Page 5

• Manufacturer Part Number: AD7927
• Description: 8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7927

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

Data Sheet
TIMING SPECIFICATIONS
AV
Table 2.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
SCLK
CONVERT
QUIET
2
3
4
5
6
7
8
9
10
11
12
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of AV
(see Figure 2). The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.
Mark/space ratio for the SCLK input is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 × V
t
back to remove the effects of charging or discharging the 50 pF capacitor. This means the time, quoted in the t
of the part and is independent of the bus loading.
3
3
4
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
DD
2
= 2.7 V to 5.25 V, V
AV
10
20
16 × t
50
10
35
40
0.4 × t
0.4 × t
10
15/45
10
5
20
1
DD
= 3 V
SCLK
SCLK
SCLK
DRIVE
Limit at T
≤ AV
1
AV
10
20
16 × t
50
10
30
40
0.4 × t
0.4 × t
10
15/35
10
5
20
1
DD
, REF
DD
MIN
= 5 V
SCLK
SCLK
SCLK
, T
IN
Figure 2. Load Circuit for Digital Output Timing Specifications
MAX
= 2.5 V; T
AD7927
TO OUTPUT
Unit
kHz min
MHz max
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min/max
ns min
ns min
ns min
μs max
A
PIN
= T
50pF
MIN
Rev. C | Page 5 of 28
C
L
to T
200µA
200µA
MAX
Description
Minimum quiet time required between CS rising edge and start of
next conversion
CS to SCLK setup time
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulsewidth
SCLK high pulsewidth
SCLK to DOUT valid hold time
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Sixteenth SCLK falling edge to CS high
Power-up time from full power-down/auto shutdown mode
, unless otherwise noted.
I
I
OL
OH
1.6V
8
DD
timing characteristics, is the true bus relinquish time
) and timed from a voltage level of 1.6 V,
DRIVE
.
AD7927