AD7927 Analog Devices, AD7927 Datasheet - Page 19

• Manufacturer Part Number: AD7927
• Description: 8-Channel, 200 kSPS, 12-Bit ADC with Sequencer in 20-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7927

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

Data Sheet
MODES OF OPERATION
The AD7927 has a number of different modes of operation,
which are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for differing application
requirements. The mode of operation of the AD7927 is con-
trolled by the power management bits, PM1 and PM0, in the
control register, as detailed in Table 8. When power supplies
are first applied to the AD7927, care should be taken to ensure
that the part is placed in the required mode of operation (see
the Powering Up the AD7927 section).
NORMAL MODE (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate perform-
ance because the user does not have to worry about any power-
up times with the AD7927 remaining fully powered at all times.
Figure 21 shows the general diagram of the operation of the
AD7927 in this mode.
The conversion is initiated on the falling edge of CS and the track-
and-hold enters hold mode as described in the Serial Interface
section. The data presented to the AD7927 on the DIN line
during the first 12 clock cycles of the data transfer are loaded
into the control register (provided the WRITE bit is 1). If data is
to be written to the shadow register (SEQ = 0, SHADOW = 1 on
the previous write), data presented on the DIN line during the
first 16 SCLK cycles is loaded into the shadow register. The part
remains fully powered up in normal mode at the end of the
conversion as long as PM1 and PM0 are set to 1 in the write
transfer during that conversion. To ensure continued operation
in normal mode, PM1 and PM0 are both loaded with 1 on
every data transfer. Sixteen serial clock cycles are required to
complete the conversion and access the conversion result. The
track-and-hold goes back into track on the 14
edge. CS may then idle high until the next conversion or may
idle low until sometime prior to the next conversion (effectively
idling CS low).
DOUT
SCLK
DIN
CS
PART IS IN FULL
SHUTDOWN
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS. PM1 = 1, PM0 = 1
1
DATA IN TO CONTROL REGISTER
PART BEGINS TO POWER UP ON
CS RISING EDGE AS PM1 = PM0 = 1
th
SCLK falling
Figure 22. Full Shutdown Mode Operation
14
Rev. C | Page 19 of 28
16
t
12
For specified performance, the throughput rate should not
exceed 200 kSPS, which means there should be no less than
5 μs between consecutive falling edges of CS when converting.
The actual frequency of SCLK used determines the duration of
the conversion within this 5 μs cycle; however, once a conversion
is complete and CS has returned high, a minimum of the quiet
time, t
another conversion.
FULL SHUTDOWN (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7927 is powered
down. The part retains information in the control register during
full shutdown. The AD7927 remains in full shutdown until the
power management bits, PM1 and PM0, in the control register
are changed.
If a write to the control register occurs while the part is in full
shutdown, with the power management bits changed to PM0 =
CS rising edge. The track-and-hold that was in hold while the
part was in full shutdown returns to track on the 14
falling edge. A full 16-SCLK transfer must occur to ensure the
control register contents are updated; however, the DOUT line
is not driven during this wake-up transfer.
To ensure that the part is fully powered up, t
elapsed before the next CS falling edge; otherwise, invalid data
is read if a conversion is initiated before this time. Figure 22 shows
the general diagram for this sequence.
THE PART IS FULLY POWERED UP
ONCE
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES.
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES.
DOUT
SCLK
t
QUIET
DIN
POWER UP
CS
1
TO KEEP THE PART IN NORMAL MODE, LOAD
PM1 = PM0 = 1 IN CONTROL REGISTER
DATA IN TO CONTROL REGISTER/SHADOW REGISTER
, must elapse before bringing CS low again to initiate
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
HAS ELAPSED
1 LEADING ZERO + 3 CHANNEL IDENTIFIER BITS
1
Figure 21. Normal Mode Operation
DATA IN TO CONTROL REGISTER/
+ CONVERSION RESULT
SHADOW REGISTER
12
POWER UP
14
16
th
16
AD7927
should have
SCLK