AD7908 Analog Devices, AD7908 Datasheet - Page 26

• Manufacturer Part Number: AD7908
• Description: 8-Channel, 1 MSPS, 8-Bit ADC with Sequencer in 20-Lead TSSOP
• Manufacturer: Analog Devices

Specifications of AD7908

• Resolution (bits): 8bit
• # Chan: 8
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: SOP

AD7908/AD7918/AD7928
AD7908/AD7918/AD7928 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7908/AD7918/AD7928 without any glue logic required. The
V
supply voltage as that of the ADSP-21xx. This allows the ADC
to operate at a higher voltage than the serial interface, that is,
ADSP-21xx, if necessary.
The SPORT0 control register should be set up as follows:
The connection diagram is shown in Figure 31. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS set
as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS , as with all signal processing applications
where equidistant sampling is necessary. However, in this
example the timer interrupt is used to control the sampling rate
of the ADC, and under certain conditions equidistant sampling
cannot be achieved.
1
1
DRIVE
ADDITIONAL PINS REMOVED FOR CLARITY.
ADDITIONAL PINS REMOVED FOR CLARITY.
TFSW = RFSW = 1, alternate framing
INVRFS = INVTFS = 1, active low frame signal
DTYPE = 00, right justify data
SLEN = 1111, 16-bit data-words
ISCLK = 1, internal serial clock
TFSR = RFSR = 1, frame every word
IRFS = 0
ITFS = 1
AD7908/
AD7918/
AD7928
AD7908/
AD7918/
AD7928
V
DRIVE
pin of the AD7908/AD7918/AD7928 takes the same
DOUT
V
SCLK
DOUT
SCLK
1
DRIVE
1
DIN
DIN
CS
CS
Figure 30. Interfacing to the TMS320C541
Figure 31. Interfacing to the ADSP-21xx
CLKX
CLKR
DR
DT
FSX
FSR
SCLK
DR
RFS
TFS
DT
V
TMS320C541
V
ADSP-21xx
DD
DD
1
1
Rev. D | Page 26 of 32
The timer register, for example, is loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and thus the
reading of data. The frequency of the serial clock is set in the
SCLKDIV register. When the instruction to transmit with TFS
is given (that is, AX0 = TX0), the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
before transmission can start. If the timer and SCLK values are
chosen, such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data can be transmitted or it
can wait until the next clock edge.
For example, if the ADSP-2189 had a 20 MHz crystal such that
it had a master clock frequency of 40 MHz, then the master
cycle time would be 25 ns. If the SCLKDIV register was loaded
with the value 3, then an SCLK of 5 MHz is obtained, and eight
master clock periods elapse for every one SCLK period.
Depending on the throughput rate selected, if the timer register
is loaded with the value, say 803 (803 + 1 = 804), 100.5 SCLKs
occur between interrupts and subsequently between transmit
instructions. This situation results in nonequidistant sampling
as the transmit instruction is occurring on a SCLK edge. If the
number of SCLKs between interrupts is a whole integer figure
of N, then equidistant sampling is implemented by the DSP.
AD7908/AD7918/AD7928 to DSP563xx
The connection diagram in Figure 32 shows how the
AD7908/AD7918/AD7928 can be connected to the synchronous
serial interface (ESSI) of the DSP563xx family of DSPs from
Motorola. Each ESSI (two on board) is operated in synchronous
mode (SYN bit in CRB = 1) with internally generated word
length frame sync for both Tx and Rx (Bit FSL1 = 0 and
Bit FSL0 = 0 in CRB). Normal operation of the ESSI is selected
by making MOD = 0 in the CRB. Set the word length to 16 by
setting Bit WL1 = 1 and Bit WL0 = 0 in CRA. The FSP bit in the
CRB should be set to 1 so the frame sync is negative. It should
be noted that for signal processing applications, it is imperative
that the frame synchronization signal from the DSP563xx
provides equidistant sampling.
In the example shown in Figure 32, the serial clock is taken
from the ESSI so the SCK0 pin must be set as an output, SCKD
= 1. The V
same supply voltage as that of the DSP563xx. This allows the
ADC to operate at a higher voltage than the serial interface, that
is, DSP563xx, if necessary.
DRIVE
pin of the AD7908/AD7918/AD7928 takes the