AD7725 Analog Devices, AD7725 Datasheet - Page 24

• Manufacturer Part Number: AD7725
• Description: 16-Bit Sigma Delta ADC with a Programmable Post Processor
• Manufacturer: Analog Devices

Specifications of AD7725

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 14.4MSPS
• Interface: Par,Ser
• Analog Input Type: Diff-Bip,SE-Uni
• Ain Range: 4 V p-p,Uni 4.0V
• Adc Architecture: Sigma-Delta
• Pkg Type: QFP

AD7725
EPROM Mode—Loading Configuration Data from an
External EPROM
In this mode, a user-defined filter can be developed off-chip, and
the resulting configuration file is loaded into the postprocessor in
the AD7725 from an External EPROM. The AD7725 therefore
receives filter data from an EPROM before outputting conversion
results via the serial interface to a DSP. This mode of operation is
selected by tying SMODE0 to DGND and SMODE1 to DV
The values on these pins inform the AD7725 that user-defined
filter data is to be loaded from an external EPROM automatically
on power-up. Following power-up, the AD7725 will drive the SOE
pin low, which will enable the EPROM and reset its address
counter. The transfer of the configuration data will then com-
mence with the data being latched into the AD7725 on the SCO
rising edge. During the download of data, SCO has a frequency of
CLKIN/16. FSI is not used in the data transfer, so it should be tied
low. Once configuration is complete and no error occurred, SOE
will go high, disabling the EPROM; SCO will return to either
CLKIN or CLKIN/2, depending on SCR; CFGEND will go high
driving the INIT pin high, and the device will start converting.
However, if an error does occur during the configuration, the ERR
bit will go low and CFGEND will not go high. The part will not
do anything until RESETCFG is pulsed low. When this occurs,
the part is reset, SOE goes low again to enable the EPROM,
and the part is reconfigured. Figure 28 shows the connection
diagram for the AD7725 when loading configuration data from
an EPROM, and Figure 29 shows a flow chart of the power-up
and configuration sequence.
S/P
0
1
1
1
1
Figure 28. Connection Diagram for Loading the
Filter Configuration Data from an External EPROM
SMODE[1, 0]
xx
00
01
10
11
DV
DV
DD
DD
SERIAL EPROM
SMODE1
ERR
CFGEND
INIT
DVAL
RESETCFG
SMODE0
SYNC
S/P
SOE
AD7725
Configuration Mode
PARALLEL
BFR
DSP
EPROM
EPROM
SCO
SDO
FSO
FSI
SDI
ADSP-21xx
SCLK0
RFS0
DR0
Table IV. Programming Modes
Description
Parallel Interface. The 16-bit bidirectional microprocessor.
Interface is used for read/write operations.
Serial Interface. Boot from the default filter (internal ROM) at
power-on reset (POR).
Serial Interface. Bidirectional serial synchronous interface
suitable for interfacing to a DSP.
Serial Interface. Boot from external serial EPROM at POR.
Serial Interface. Boot from external serial EPROM at POR.
DD
.
–24–
Boot from ROM Mode (BFR)—Using the Internal
Default Filter
This mode of operation allows the user to evaluate the AD7725
without having to load configuration data. It is selected by tying
SMODE0 and SMODE1 to DGND. The values on these pins
inform the AD7725 that the postprocessor is to be configured
with the default filter stored in internal ROM. The default filter
data will be loaded into the postprocessor automatically following
power-up. Once the configuration is complete, the CFGEND pin
will go high. In Figure 30, CFGEND is tied to INIT, thus it will
drive the INIT pin high, and the AD7725 will begin converting.
FSI and SDI are not used in this mode, so they should be tied
to DGND. In this mode of operation, the AD7725 operates as a
normal - ADC with a fixed filter response.
During configuration, SCO will have a frequency of CLKIN/16.
Once configuration is complete, the frequency of SCO is selected
by SCR and will be either CLKIN or CLKIN/2. Additionally,
the SCO edge on which the data is output from the device can
be selected using CFMT. With SCR = 0, SCO equals CLKIN.
With SCR = 1, SCO equals CLKIN/2. With CFMT = 0, data is
output on the SCO rising edge, while data is output on the
falling edge when CFMT = 1. Figure 30 shows the connection
diagram for the AD7725 when using the internal default filter,
and Figure 31 shows a flow chart of the power-up and configu-
ration sequence.
Figure 29. Flow Chart of EPROM Mode
USER-DEFINED FILTER
DATA LOADED INTO
THE POSTPROCESSOR
FROM EPROM
POWER-ON RESET
DEVICE STARTS
IMMEDIATE BOOT
FROM AN EPROM
CORRECTLY?
CONVERTING
LOADED
YES
DATA
SOE GOES LOW
SOE GOES HIGH
CFGEND = 1
INIT = 1
NO
ERR = 0
SMODE0 = 0
SMODE1 = 1
RESETCFG
PULSE
LOW
REV. A