AD7725 Analog Devices, AD7725 Datasheet
AD7725
Specifications of AD7725
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AD7725 Summary of contents
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... SDI/DB0 Filter Wizard allows the user to design different filter types and generates the appropriate configuration file to be down- loaded to the postprocessor. The AD7725 also has an internal default filter for evaluation purposes. It provides 16-bit performance for input bandwidths up to 350 kHz with an output word rate of 900 kHz maximum. The input sample rate is set either by the crystal oscillator or an external clock ...
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... AD7725–SPECIFICATIONS Parameter DYNAMIC SPECIFICATIONS Bipolar Mode 3 Signal-to-Noise 3, 5 Total Harmonic Distortion 3, 5 Spurious Free Dynamic Range Unipolar Mode 3 Signal-to-Noise 3, 5 Total Harmonic Distortion ANALOG INPUTS Full-Scale Input Span Bipolar Mode Unipolar Mode Absolute Input Voltage Input Sampling Capacitance ...
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... AGND2. At frequencies below 10 kHz, THD degrades to –80 dB and SFDR degrades to –83 dB. 6 See Figures 23 and 24 for information regarding the number of filter taps allowed and the current consumption as the CLKIN frequency is varied. 7 The AD7725 can operate with an external reference input in the range Guaranteed by the design. 9 Gain Error excludes reference error ...
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... AD7725 Preset Filter, Default Filter, and Postprocessor Characteristics Parameter Test Conditions/Comments DIGITAL FILTER RESPONSE PRESET FIR Data Output Rate Stop-Band Attenuation Low-Pass Corner Frequency 3 Group Delay 3 Settling Time DEFAULT FILTER Internal FIR Filter Stored in ROM Number of Taps Frequency Response 0 kHz to f /546.08 ...
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... CLK 2 t CLK CLK 8 t CLK 20 t CLK CLK and timed from a voltage level of 1 AD7725 ...
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... AD7725 Figure 2. Load Circuit for Digital Output Timing Specifications t 5 2.3V CLKIN 0. SCO SCR = SCO SCR = 1 SCO CFMT = FSI SDI FSO SDO Figure 4. Serial Mode (DSP Mode and Boot from ROM (BFR) Mode). In BFR Mode, FSI and SDI are not used. ...
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... INT RD/ DB0 DB15 – Figure 6. Parallel Mode (Writing Data to the AD7725) INT RD/ DB0 DB15 – Figure 7. Parallel Mode (Reading Data from the AD7725) REV SCO SCO t 19 SDI Figure 5. Serial Mode (EPROM Mode ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7725 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Parallel Mode. RS–Register Select. RS selects between the data register, used to read conversion data or write configuration data, and the instruction register. When RS is high, the status register can be read or an instruction can be written to the AD7725. When RS is low, data such as the configuration file can be written to the ADC while data such as the device conversion result can be read from the AD7725 (see Table I) ...
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... M resistor, can be connected between the XTAL pin and the CLKIN pin with XTALOFF tied low. External capacitors are then required from the CLKIN and XTAL pins to ground. Consult the crystal manufacturer’s recommendation for the load capacitors. In both cases, once power is applied to the AD7725, the clock input has to be continual. 13 XTAL Input to Crystal Oscillator Amplifier ...
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... RS input) into the AD7725. In this case, the data should be set up for a time t the CS rising edge. Serial Mode. SMODE1–Serial Mode Select, Logic Input. This pin selects the serial mode to be used (see Table IV) and thus informs the device where to download configuration data from automatically on power up ...
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... DGND/DB3 Description Serial Mode. SDO–Serial Data Output. The serial data is shifted out of the AD7725 MSB first, in twos complement format, synchronous with SCO. Parallel Mode. DB8–Data Input/Output Bit. Digital Power Supply Voltage. Serial Mode. SCO–Serial Clock Output. The frequency of SCO is a function of the CLKIN frequency and is set by the SCR pin ...
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... The settling time for each filter stage should be calculated separately and then added to get the total filter settling time. Group delay is half the settling time. –13– AD7725 ...
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... AD7725–Typical Performance Characteristics PERFORMANCE PLOTS The following typical plots are generated using the digital filter shown in Figure 1. ( CLKIN = 9.6 MHz, External Reference = 2.5 V, unless otherwise noted 110 INPUT FREQUENCY = 10kHz 100 90 80 SFDR THD –50 –40 – ...
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... CLKIN technique to sample the input signal. For the purpose of driving the AD7725, an equivalent circuit of the analog inputs is shown in Figure 11. For each half-clock cycle, two highly linear sam- pling capacitors are switched to both inputs, converting the input signal into an equivalent sampled charge. A signal source ...
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... CLKIN Figure 11. Analog Input Equivalent Circuit Driving the Analog Inputs To interface the signal source to the AD7725, at least one op amp will generally be required. The choice of op amp will be critical to achieving the full performance of the AD7725. The op amp not only has to recover from the transient loads that the ADC imposes on it, but it must also have good distortion char- acteristics and very low input noise ...
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... ADC. In both cases, the clock input has to be continual; once power is applied to the AD7725, it has to be continually clocked. The connection diagram for use with a crystal is shown in Figure 18. Consult the manufacturer’s recommendation for the load capacitors ...
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... The data is passed between processors and, in this manner, complex opera- tions are performed on the input signal. In the AD7725, data transfers between processors are fully synchronous result, the user does not have to consider timing issues. ...
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... C 3 Using the Internal Default Filter The AD7725 has a default filter stored in internal ROM that can be loaded into the postprocessor. This functionality allows the user to evaluate the device without having to download a configuration file. The default filter is a two-stage, low-pass, FIR – ...
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... Therefore, with suitable deci- mation, the SNR will typically at the AD7725 output. Decimating the data rate allows an improvement in the filter transition width equal to the inverse of the decimation factor. ...
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... DD the filter is increased. MODES OF OPERATION The AD7725 can operate with either a serial or a parallel interface. These modes are chosen by setting the logic state of the S/P pin. REV. A PARALLEL MODE The parallel mode is selected by tying S/P to DGND. Pro- gramming the postprocessor and operation of the AD7725 in parallel mode requires the use of an instruction set ...
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... BFR 0x2000 Boot from Internal ROM Configuring the Device Following power-up, the AD7725 is configured by loading a user- defined filter from an external source via the parallel interface. Three instructions are provided for configuring the AD7725 (see Table III). • WrConfig (Write Configuration) ...
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... The FSI and FSO signals are used to indicate to either the device or the processor, the beginning of a word transmission into or out of the device. The AD7725 provides the clock for conversion and data transfers. The CFMT pin selects the active edge of SCO during conversions and the EFMT pin selects the active edge of SCO during configuration ...
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... EPROM and reset its address counter. The transfer of the configuration data will then com- mence with the data being latched into the AD7725 on the SCO rising edge. During the download of data, SCO has a frequency of CLKIN/16. FSI is not used in the data transfer should be tied low. Once configuration is complete and no error occurred, SOE will go high, disabling the EPROM ...
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... FSO and SDO from each device separately. Daisy-Chaining—Configuration and Conversion Data Several AD7725s can be daisy-chained so that they are con- figured from a common external serial EPROM or DSP (as discussed earlier in Daisy-Chaining during Configuration), and all conversion data from each individual device can be read back by a single DSP on one serial data stream ...
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... Figure 34. Daisy-Chaining Devices with a Common DSP and a Shared EPROM Cascading Filters across Multiple Devices If the design of a filter is too large for one AD7725 device to handle, the filter can be cascaded across multiple devices. For example, if you have a 3-stage filter in your design that requires over 108 taps to be implemented, this filter can be shared between two or three devices ...
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... The analog ground plane should be allowed to run under the AD7725 to shield it from noise coupling. The power supply lines to the AD7725 should use as large a trace as possible (preferably a plane) to provide a low impedance path and reduce the effects of glitches on the power supply line. ...
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... AD7725 2.10 2.00 1.95 0.25 MIN VIEW A ROTATED 90 CCW Revision History Location 2/04—Data Sheet changed from REV REV. A Changes to title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to Figure Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Changes to Figure Changes to Figure Changes to DSP Mode—Loading Configuration Data from a DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Changes to EPROM Mode— ...