AD7921 Analog Devices, AD7921 Datasheet - Page 21

• Manufacturer Part Number: AD7921
• Description: 2-Channel, 2.35 V to 5.25 V, 250 kSPS, 12-Bit A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7921

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

SERIAL INTERFACE
Figure 30 and Figure 31 show the detailed timing diagrams for
serial interfacing to the AD7921 and AD7911, respectively. The
serial clock provides the conversion clock and also controls the
transfer of information from the AD7911/AD7921 during
conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode,
takes the bus out of three-state, the analog input is sampled at
this point, and the conversion is initiated.
For the AD7921, the conversion requires 16 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 30 at Point B. On the 16th SCLK falling edge,
the DOUT line goes back into three-state. If the rising edge of
CS occurs before 16 SCLKs have elapsed, then the conversion is
terminated and the DOUT line goes back into three-state.
Otherwise, DOUT returns to three-state on the 16th SCLK
falling edge, as shown in
are required to perform the conversion process and to access
data from the AD7921.
For the AD7911, the conversion requires 14 SCLK cycles to
complete. Once 13 SCLK falling edges have elapsed, the track-
and-hold goes back into track on the next SCLK rising edge, as
shown in Figure 31 at Point B.
DOUT
DOUT
SCLK
SCLK
DIN
DIN
CS
CS
THREE-STATE
THREE-STATE
Figure 30
t
t
2
2
X
X
Z
Z
1
1
t
ZERO
t
ZERO
3
3
. Sixteen serial clock cycles
X
X
2
2
CHN
CHN
t
t
CHN
CHN
8
8
3
3
X
X
t
Figure 30. AD7921 Serial Interface Timing Diagram
Figure 31. AD7911 Serial Interface Timing Diagram
CONVERT
X
X
t
t
4
9
4
9
DB11
DB9
t
t
t
t
6
6
4
4
t
X
X
CONVERT
5
5
t
t
DB10
7
7
DB8
Rev. A | Page 21 of 28
X
X
13
13
If the rising edge of CS occurs before 14 SCLKs have elapsed,
then the conversion is terminated and the DOUT line goes back
into three-state. If 16 SCLKs are considered in the cycle, DOUT
returns to three-state on the 16th SCLK falling edge, as shown
in
CS going low clocks out the first leading zero to be read in by
the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges beginning with the
second leading zero. Therefore, the first falling clock edge on
the serial clock has the first leading zero provided and also
clocks out the second leading zero. The final bit in the data
transfer is valid on the 16th falling edge, having been clocked
out on the previous (15th) falling edge.
In applications with a slower SCLK, it is possible to read in data
on each SCLK rising edge. In that case, the first falling edge of
SCLK clocks out the second leading zero and it can be read in
the first rising edge. However, the first leading zero that is
clocked out when CS goes low is missed, unless it is not read in
the first falling edge. The 15th falling edge of SCLK clocks out
the last bit and it can be read in the 15th rising SCLK edge.
If CS goes low just after the SCLK falling edge has elapsed, CS
clocks out the first leading zero as before and it can be read in
the SCLK rising edge. The next SCLK falling edge clocks out
the second leading zero and it can be read in the following
rising edge.
DB2
DB0
B
B
TWO TRAILING ZEROS
Figure 31
X
X
14
14
t
t
5
5
ZERO
DB1
X
X
.
15
15
ZERO
DB0
X
X
16
THREE-STATE
16
THREE-STATE
t
t
10
10
t
t
QUIET
QUIET
t
t
1
1
AD7911/AD7921