AD7921 Analog Devices, AD7921 Datasheet - Page 15

• Manufacturer Part Number: AD7921
• Description: 2-Channel, 2.35 V to 5.25 V, 250 kSPS, 12-Bit A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7921

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: SE-Uni
• Ain Range: Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOP,SOT

CIRCUIT INFORMATION
The AD7911/AD7921 are fast, 2-channel, 10-/12-bit, single
supply, analog-to-digital converters (ADCs), respectively. The
parts can be operated from a 2.35 V to 5.25 V supply. When
operated from either a 5 V supply or a 3 V supply, the
AD7911/AD7921 are capable of throughput rates of 250 kSPS
when provided with a 5 MHz clock.
The AD7911/AD7921 provide the user with an on-chip track-
and-hold, an ADC, and a serial interface, all housed in a tiny 8-
lead TSOT package or an 8-lead MSOP package, which offer
the user considerable space-saving advantages over alternative
solutions. The serial clock input accesses data from the parts,
controls the transfer of data written to the ADC, and provides
the clock source for the successive approximation ADC. The
analog input range is 0 to V
required for the ADC, and neither is there a reference on-chip.
The reference for the AD7911/AD7921 is derived from the
power supply and, therefore, gives the widest dynamic input
range.
The AD7911/AD7921 feature a power-down option that allows
power saving between conversions. The power-down feature is
implemented across the standard serial interface as described in
the Modes of Operation section.
CONVERTER OPERATION
The AD7911/AD7921 are 10-/12-bit successive approximation
ADCs based around a charge redistribution DAC. Figure 19 and
Figure 20 show simplified schematics of the ADC. Figure 19
shows the ADC during its acquisition phase. SW2 is closed and
SW1 is in Position A, the comparator is held in a balanced
condition, and the sampling capacitor acquires the signal on the
selected V
V
V
IN0
IN1
IN
channel.
SW1
A
AGND
B
Figure 19. ADC Acquisition Phase
CAPACITOR
SAMPLING
ACQUISITION
PHASE
V
DD
DD
/2
. An external reference is not
SW2
COMPARATOR
REDISTRIBUTION
CHARGE
CONTROL
DAC
LOGIC
Rev. A | Page 15 of 28
When the ADC starts a conversion (see Figure 20), SW2 opens
and SW1 moves to Position B, causing the comparator to
become unbalanced. The control logic and the charge
redistribution DAC are used to add and subtract fixed amounts
of charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. Figure 21 shows the ADC
transfer function.
V
V
ADC TRANSFER FUNCTION
The output coding of the AD7911/AD7921 is straight binary.
The designed code transitions occur at the successive integer
LSB values, that is, 1 LSB, 2 LSB, and so on. The LSB size is
V
ideal transfer characteristic for the AD7911/AD7921 is shown
in Figure 21.
IN0
IN1
DD
/4096 for the AD7921 and V
Figure 21. AD7911/AD7921 Transfer Characteristic
111...111
111...110
111...000
011...111
000...010
000...001
000...000
SW1
A
AGND
B
Figure 20. ADC Conversion Phase
CAPACITOR
SAMPLING
0V
CONVERSION
1LSB
PHASE
V
DD
/2
ANALOG INPUT
1LSB = V
1LSB = V
DD
SW2
/1024 for the AD7911. The
COMPARATOR
DD
DD
AD7911/AD7921
/4096 (AD7921)
/1024 (AD7911)
+V
DD
REDISTRIBUTION
– 1LSB
CHARGE
CONTROL
DAC
LOGIC