AD7938-6 Analog Devices, AD7938-6 Datasheet - Page 21

• Manufacturer Part Number: AD7938-6
• Description: 8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938-6

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 625kSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Uni (Vref),Uni (Vref) x 2
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

Data Sheet
Using the Sequencer: Programmable Sequence
(SEQ = 0, SHDW = 1 )
The AD7938-6 can be configured to automatically cycle through a
number of selected channels using the on-chip programmable
sequencer by setting SEQ = 0 and SHDW = 1 in the control
register. The analog input channels to be converted are selected
by setting the relevant bits in the shadow register to 1 (see
Table 11).
Once the shadow register has been programmed with the required
sequence, the next conversion executed is on the lowest channel
programmed in the SHDW register. The next conversion
executed is on the next highest channel in the sequence, and so
on. When the last channel in the sequence is converted, the
internal multiplexer returns to the first channel selected in the
shadow register and commences the sequence again.
It is not necessary to write to the control register again once a
sequencer operation has been initiated. The WR input must be
kept high to ensure that the control register is not accidentally
overwritten or that a sequence operation is not interrupted.
If the control register is written to at any time during the
sequence, ensure that the SEQ and SHDW bits are set
to 1, 0 to avoid interrupting the conversion sequence. The
sequence program remains in force until such time as the
AD7938-6 is written to and the SEQ and SHDW bits are
configured with any bit combination except 1, 0.
shows a flow chart of the programmable sequence operation.
Consecutive Sequence (SEQ = 1, SHDW = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0 and ending with a final channel selected by
writing to the ADD2 to ADD0 bits in the control register.
This is done by setting the SEQ and SHDW bits in the control
register to 1. In this mode, the sequencer can be used without
having to write to the shadow register. In this mode, once the
THIS WRITE CYCLE IS TO PROGRAM THE SHADOW REGISTER.
WITH EACH CONVST PULSE.
IN THE SHADOW REGISTER
CONTINUOUSLY CONVERT
CHANNELS SELECTED
THE CHANNELS TO BE INCLUDED IN THE SEQUENCE.
CONSECUTIVE
Figure 31. Programmable Sequence Flow Chart
SET UP OPERATING MODE, ANALOG INPUT
SHDW BIT = 1
WRITE TO THE CONTROL REGISTER TO
SEQ BIT = 0
WR = HIGH
SET RELEVANT BITS TO SELECT
AND OUTPUT CONFIGURATION
INITIATE A WRITE CYCLE.
SET SEQ = 0 SHDW = 1.
POWER ON
CODING, ANALOG INPUT TYPE,
WITH EACH CONVST PULSE
REGISTER TO BE CHANGED
ETC BITS IN THE CONTROL
CONTINUOUSLY CONVERT
BUT ALLOWS THE RANGE,
WITHOUT INTERRUPTING
SEQ BIT = 1
SHDW BIT = 0
CHANNELS SELECTED
THE SEQUENCE.
CONSECUTIVE
Figure 31
Rev. C | Page 21 of 32
control register is written to, the next conversion is on Channel
0, then Channel 1, and so on until the channel selected by the
address bits (ADD2 to ADD0) is reached. The cycle begins
again provided the WR input is tied high. If low, the SEQ and
SHDW bits must be set to 1, 0 to allow the ADC to continue its
preprogrammed sequence uninterrupted.
flow chart of the consecutive sequence mode.
REFERENCE
The AD7938-6 can operate with either the on-chip reference or
external reference. The internal reference is selected by setting
the REF bit in the internal control register to 1. A block diagram
of the internal reference circuitry is shown in Figure 33. The
internal reference circuitry includes an on-chip 2.5 V band gap
reference and a reference buffer. When using the internal
reference, the V
with a 0.47 μF capacitor. This internal reference not only
provides the reference for the analog-to-digital conversion, but
it can also be used externally in the system. It is recommended
that the reference output be buffered using an external precision
op amp before applying it anywhere in the system.
Alternatively, an external reference can be applied to the
V
is selected by setting the REF bit in the internal control register
to 0. The external reference input range is 0.1 V to V
important to ensure that, when choosing the reference value,
the maximum analog input range (V
V
REFIN
DD
+ 0.3 V to comply with the maximum ratings of the device.
/V
REFOUT
Figure 33. Internal Reference Circuit Block Diagram
Figure 32. Consecutive Sequence Mode Flow Chart
V
V
REFOUT
REFIN
SELECTED FINAL CHANNEL ON ADD2 TO ADD0
pin of the AD7938-6. An external reference input
SEQUENCE OF CHANNELS FROM CHANNEL 0
CONTINUOUSLY CONVERT A CONSECUTIVE
SET UP OPERATING MODE, ANALOG INPUT
REFIN
UP TO AND INCLUDING THE PREVIOUSLY
ALLOWS THE RANGE, CODING, ANALOG
WRITE TO THE CONTROL REGISTER TO
AND OUTPUT CONFIGURATION SELECT
/
CONTROL REGISTER TO BE CHANGED
CONSECUTIVE CHANNELS SELECTED
FINAL CHANNEL (ADD2 TO ADD0) IN
WITH EACH CONVST PULSE BUT
/V
INPUT TYPE, ETC BITS IN THE
WITH EACH CONVST PULSE.
CONSECUTIVE SEQUENCE.
CONTINUOUSLY CONVERT
REFOUT
WITHOUT INTERRUPTING
SET SEQ = 1 SHDW = 1.
BUFFER
THE SEQUENCE.
POWER ON
pin should be decoupled to AGND
SEQ BIT = 1
SHDW BIT = 0
ADC
IN MAX
REFERENCE
AD7938-6
) is never greater than
Figure 32
AD7938-6
shows the
DD
. It is