AD7938 Analog Devices, AD7938 Datasheet - Page 30

• Manufacturer Part Number: AD7938
• Description: 8-Channel, 1.5 MSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

AD7938/AD7939
AD7938/AD7939 to ADSP-21065L Interface
Figure 44 shows a typical interface between the
AD7938/AD7939 and the
This interface is an example of one of three DMA handshake
modes. The MS
lines. Internal ADDR
lines are then asserted as chip selects. The DMAR
request 1) is used in this setup as the interrupt to signal the end
of conversion. The rest of the interface is a standard
handshaking operation.
AD7938/AD7939 to TMS32020, TMS320C25, and
TMS320C5x Interface
Parallel interfaces between the AD7938/AD7939 and the
TMS32020, TMS320C25, and TMS320C5x family of DSPs are
shown in Figure 45. The memory mapped address chosen for
the AD7938/AD7939 should be chosen to fall in the I/O
memory space of the DSPs. The parallel interface on the
AD7938/AD7939 is fast enough to interface to the TMS32020
with no extra wait states. If high speed glue logic, such as 74AS
devices, is used to drive the RD and the WR lines when
interfacing to the TMS320C25, no wait states are necessary.
However, if slower logic is used, data accesses can be slowed
sufficiently when reading from, and writing to, the part to
require the insertion of one wait state. Extra wait states are
necessary when using the TMS320C5x at their fastest clock
speeds (see the TMS320C5x User’s Guide for details).
Data is read from the ADC using the following instruction
where:
D is the data memory address.
ADC is the AD7938/AD7939 address.
*ADDITIONAL PINS OMITTED FOR CLARITY.
ADDR
ADSP-21065L*
IN D, ADC
0
TO ADDR
D0 TO D31
DMAR
MS
WR
RD
23
Figure 44. Interfacing to the ADSP-21065L
X
1
X
control line is actually three memory select
ADDRESS BUS
25-24
DECODER
ADDRESS
ADDRESS
DATA BUS
LATCH
are decoded into MS
ADSP-21065L
ADDRESS BUS
SHARC® processor.
DSP/USER SYSTEM
3 to 0
CS
BUSY
RD
WR
DB0 TO DB11
AD7938/
AD7939*
, and these
1
CONVST
(DMA
Rev. C | Page 30 of 36
AD7938/AD7939 to 80C186 Interface
Figure 46 shows the AD7938/AD7939 interfaced to the 80C186
microprocessor. The 80C186 DMA controller provides two
independent high speed DMA channels where data transfer can
occur between memory and I/O spaces. Each data transfer
consumes two bus cycles, one cycle to fetch data and the other
to store data. After the AD7938/AD7939 finish a conversion,
the BUSY line generates a DMA request to Channel 1 (DRQ1).
Because of the interrupt, the processor performs a DMA read
operation that also resets the interrupt latch. Sufficient priority
must be assigned to the DMA channel to ensure that the DMA
request is serviced before the completion of the next conversion.
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
DMD0 TO DMD15
TMS320C25/
TMS320C50*
TMS32020/
80C186*
AD0 TO AD15
Figure 45. Interfacing to the TMS32020/TMS320C25/TMS320C5x
A16 TO A19
A0 TO A15
DRQ1
READY
ALE
WR
STRB
RD
MSC
INT
R/W
IS
X
ADDRESS/DATA BUS
Figure 46. Interfacing to the 80C186
DECODER
ADDRESS
ADDRESS
Q R
ADDRESS BUS
EN
LATCH
S
ADDRESS
DECODER
ADDRESS BUS
DATA BUS
TMS320C25
ONLY
DATA BUS
DSP/USER SYSTEM
CS
WR
RD
BUSY
DB11 TO DB0
Data Sheet
MICROPROCESSOR/
CS
BUSY
RD
WR
DB0 TO DB11
AD7938/
AD7939*
USER SYSTEM
CONVST
AD7938/
AD7939*
CONVST