AD7938 Analog Devices, AD7938 Datasheet - Page 29

• Manufacturer Part Number: AD7938
• Description: 8-Channel, 1.5 MSPS, 12-Bit Parallel ADCs with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7938

• Resolution (bits): 12bit
• # Chan: 8
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: CSP,QFP

Data Sheet
POWER vs. THROUGHPUT RATE
A considerable advantage of powering the ADC down after a
conversion is that the power consumption of the part is
significantly reduced at lower throughput rates. When using the
different power modes, the AD7938/AD7939 are only powered
up for the duration of the conversion. Therefore, the average
power consumption per cycle is significantly reduced. Figure 41
shows a plot of the power vs. throughput rate when operating in
autostandby mode for both V
the maximum CLKIN frequency of 25.5 MHz is used to
minimize the conversion time, this accounts for only 0.525 µs of
the overall cycle time while the AD7938/AD7939 remains in
standby mode for the remainder of the cycle. If the devices run
at a throughput rate of 10 kSPS, for example, the overall cycle
time is 100 µs.
Figure 42 shows a plot of the power vs. throughput rate when
operating in normal mode for both V
both plots, the figures apply when using the internal reference.
If an external reference is used, the power-up time reduces to
600 ns; therefore, the AD7938/AD7939 remain in standby for a
greater time in every cycle. Additionally, the current consumption,
when converting, should be lower than the specified maximum
of 2.7 mA with V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
T
A
Autostandby Mode Using Internal Reference
= 25°C
20
DD
Figure 41. Power vs. Throughput in
= 5 V, or 2.0 mA with V
40
THROUGHPUT (kSPS)
DD
60
= 5 V and 3 V. For example, if
80
DD
= 5 V and V
100
DD
V
V
DD
DD
= 3 V.
= 5V
= 3V
120
DD
= 3 V. In
140
Rev. C | Page 29 of 36
MICROPROCESSOR INTERFACING
AD7938/AD7939 to ADSP-21xx Interface
Figure 43 shows the AD7938/AD7939 interfaced to the ADSP-
21xx series of DSPs as a memory-mapped device. A single wait
state may be necessary to interface the AD7938/AD7939 to the
ADSP-21xx depending on the clock speed of the DSP. The wait
state can be programmed via the data memory wait state
control register of the ADSP-21xx (see the ADSP-21xx family
User’s Manual for details). The following instruction reads from
the AD7938/AD7939:
where ADC is the address of the AD7938/AD7939.
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 42. Power vs. Throughput in Normal Mode Using Internal Reference
ADSP-21xx*
MR = DM (ADC)
A0 TO A15
D0 TO D23
10
9
8
7
6
5
4
3
2
1
0
0
IRQ2
DMS
T
WR
A
RD
= 25°C
200
Figure 43. Interfacing to the ADSP-21xx
ADDRESS BUS
400
ADDRESS
DECODER
DATA BUS
THROUGHPUT (kSPS)
600
800
AD7938/AD7939
1000
V
V
DD
DD
1200
DSP/USER SYSTEM
CS
BUSY
WR
RD
DB0 TO DB11
= 5V
= 3V
AD7938/
AD7939*
CONVST
1400
1600