AD7683 Analog Devices, AD7683 Datasheet - Page 14

• Manufacturer Part Number: AD7683
• Manufacturer: Analog Devices

Specifications of AD7683

• Resolution (bits): 16bit
• # Chan: 1
• Sample Rate: 100kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7683
VOLTAGE REFERENCE INPUT
The AD7683 voltage reference input, REF, has a dynamic input
impedance. Therefore, it should be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source (such as
an unbuffered reference voltage like the low temperature drift
ADR43x
the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is
appropriate for optimum performance.
If desired, smaller reference decoupling capacitors with values
as low as 2.2 μF can be used with a minimal impact on perfor-
mance, especially DNL.
POWER SUPPLY
The AD7683 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 24. This makes the part
ideal for low sampling rates (even of a few Hz) and low battery-
powered applications.
DIGITAL INTERFACE
The AD7683 is compatible with SPI®, QSPI™, digital hosts,
MICROWIRE™, and DSPs (for example, Blackfin®
or ADSP-219x). The connection diagram is shown in Figure 25
and the corresponding timing is given in Figure 2.
A falling edge on CS initiates a conversion and the data transfer.
After the fifth DCLOCK falling edge, D
low. The data bits are then clocked, MSB first, by subsequent
1000
0.01
100
0.1
10
1
reference or a reference buffer using the
10
Figure 24. Operating Current vs. Sampling Rate
100
SAMPLING RATE (SPS)
1k
VDD = 5V
OUT
VDD = 2.7V
is enabled and forced
10k
AD8031
ADSP-BF53x
100k
or
Rev. A | Page 14 of 16
DCLOCK falling edges. The data is valid on both DCLOCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the DCLOCK falling edge allows a
faster reading rate, provided it has an acceptable hold time.
LAYOUT
Design the PCB that houses the AD7683 so that the analog and
digital sections are separated and confined to certain areas of
the board. The pin configuration of the AD7683, with all its
analog signals on the left side and all its digital signals on the
right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7683 is used as a shield. Fast switching signals, such as CS
or clocks, should never run near analog signal paths. Avoid
crossover of digital and analog signals.
Use at least one ground plane. It can be common or split between
the digital and analog sections. In such a case, it should be joined
underneath the AD7683.
The AD7683 voltage reference input (REF) has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. Accomplish this by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, decouple the power supply, VDD, of the AD7683 with a
ceramic capacitor, typically 100 nF, placed close to the AD7683.
Connect it using short and large traces to provide low impedance
paths and reduce the effect of glitches on the power supply lines.
EVALUATING THE AD7683 PERFORMANCE
Other recommended layouts for the AD7683 are outlined in the
evaluation board for the AD7683 (EVAL-AD7683CBZ). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the
AD7683
DCLOCK
CS
Figure 25. Connection Diagram
D
OUT
EVAL-CONTROL
CLK
CONVERT
DATA IN
DIGITAL HOST
BRD3Z.