AD7942 Analog Devices, AD7942 Datasheet - Page 18

• Manufacturer Part Number: AD7942
• Manufacturer: Analog Devices

Specifications of AD7942

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7942
CS Mode 3-Wire with Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input. The connection diagram is shown in Figure 32 and the
corresponding timing diagram is shown in Figure 33.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the CS mode, and forces SDO to high impedance.
SDO is maintained in high impedance until the completion of
the conversion irrespective of the state of CNV. Prior to the
minimum conversion time, CNV can be used to select other
SPI devices, such as analog multiplexers. However, CNV must
be returned low before the minimum conversion time and held
SDI = 1
ACQUISITION
SDO
CNV
SCK
CONVERSION
Figure 33. CS Mode 3-Wire with Busy Indicator, Serial Interface Timing (SDI High)
t
CONV
t
CNVH
VIO
SDI
Figure 32. CS Mode 3-Wire with Busy Indicator
AD7942
CNV
SCK
Connection Diagram (SDI High)
1
Rev. B | Page 18 of 24
t
t
SDO
HSDO
DSDO
D13
t
2
CYC
VIO
ACQUISITION
47kΩ
D12
t
low until the maximum conversion time to guarantee the
generation of the busy signal indicator. When the conversion
is complete, SDO goes from high impedance to low impedance.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data reading controlled by the
digital host. The AD7942 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After
the optional 15th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
3
ACQ
CONVERT
DATA IN
IRQ
CLK
DIGITAL HOST
t
SCKL
t
SCKH
13
t
SCK
14
D1
15
D0
t
DIS