AD7942 Analog Devices, AD7942 Datasheet - Page 17

• Manufacturer Part Number: AD7942
• Manufacturer: Analog Devices

Specifications of AD7942

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 250kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p,Uni (Vref)
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

CS Mode 3-Wire Without Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 30 and the corresponding timing
diagram is shown in Figure 31.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the CS mode, and forces SDO to high impedance.
When a conversion is initiated, it continues to completion irres-
pective of the state of CNV. For instance, it is useful to bring
CNV low to select other SPI devices, such as analog
multiplexers. However, CNV must be returned high before the
ACQUISITION
SDI = 1
CNV
SCK
SDO
t
CNVH
Figure 31. CS Mode 3-Wire Without Busy Indicator, Serial Interface Timing (SDI High)
CONVERSION
t
CONV
VIO
Figure 30. CS Mode 3-Wire Without Busy Indicator
SDI
AD7942
t
EN
CNV
SCK
Connection Diagram (SDI High)
D13
1
Rev. B | Page 17 of 24
t
SDO
HSDO
D12
2
t
CYC
ACQUISITION
D11
minimum conversion time and held high until the maximum
conversion time to avoid generating the busy signal indicator.
When the conversion is complete the AD7942 enters the acqui-
sition phase and powers down. When CNV goes low, the MSB
is output onto SDO. The remaining data bits are then clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
14th SCK falling edge or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
t
3
ACQ
t
DSDO
CONVERT
DATA IN
CLK
DIGITAL HOST
t
SCKL
t
SCKH
12
t
SCK
13
D1
14
D0
t
DIS
AD7942