AD7946 Analog Devices, AD7946 Datasheet - Page 22

• Manufacturer Part Number: AD7946
• Manufacturer: Analog Devices

Specifications of AD7946

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

AD7946
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7946s on a
3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7946s is shown
in Figure 43, and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near-end ADC (ADC C in
ACQUISITION
SDO
SDO
CNV = SDI
t
HSCKCNV
A
B
SCK
= SDI
= SDI
SDO
B
C
C
A
SDI
CONVERSION
t
t
DSDOSDI
t
SSCKCNV
t
AD7946
CONV
DSDOSDI
t
EN
CNV
SCK
A
SDO
t
t
t
SSDISCK
HSDO
DSDO
1
D
D
D
C
A
B
2
13 D
13 D
13 D
Figure 44. Chain Mode with BUSY Indicator Serial Interface Timing
Figure 43. Chain Mode with BUSY Indicator Connection Diagram
C
A
3
B
12 D
12 D
12 D
t
SDI
SCKH
C
t
A
B
4
HSDISCK
11
11
11
AD7946
CNV
SCK
B
13
t
SCK
Rev. A | Page 22 of 24
D
D
D
SDO
14
C
A
B
1
1
1
t
SCKL
D
D
D
15
C
A
B
0
0
0 D
D
ACQUISITION
16
B
A
13 D
13 D
t
CYC
Figure 43) SDO is driven high. This transition on SDO can
be used as a BUSY indicator to trigger the data readback
controlled by the digital host. The AD7946 then enters the
acquisition phase and powers down. The data bits stored in
the internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 14 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. For instance, with a
3 ns digital host setup time and 3 V interface, up to four AD7946s
running at a conversion rate of 360 kSPS can be daisy-chained
to a single 3-wire port.
17
B
SDI
A
t
12
12
ACQ
AD7946
CNV
SCK
27
C
D
D
28
B
A
SDO
1
1
D
D
29
B
A
0 D
0
30
A
13
D
31
A
12
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
41
t
DSDOSDI
D
42
t
DSDOSDI
A
t
1
DSDOSDI
D
43
A
0