AD7946 Analog Devices, AD7946 Datasheet - Page 21

• Manufacturer Part Number: AD7946
• Manufacturer: Analog Devices

Specifications of AD7946

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

CHAIN MODE, NO BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7946s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7946s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
SDO
ACQUISITION
SDI
A
t
= SDI
HSCKCNV
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
t
t
HSDO
DSDO
AD7946
CNV
SCK
A
Figure 42. Chain Mode, No BUSY Indicator Serial Interface Timing
D
D
Figure 41. Chain Mode, No BUSY Indicator Connection Diagram
1
A
B
13
13
t
SSDISCK
SDO
D
D
2
A
B
12
12
D
D
3
A
B
11
11
Rev. A | Page 21 of 24
t
SCKL
SDI
t
HSDISCK
12
AD7946
CNV
SCK
B
t
D
D
13
CYC
A
B
onto SDO, and the AD7946 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 14 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. The maximum conver-
sion rate may be reduced due to the total readback time. For
instance, with a 3 ns digital host setup time and 3 V interface,
up to four AD7946s running at a conversion rate of 360 kSPS
can be daisy-chained on a 3-wire port.
1
1
ACQUISITION
t
SDO
SCK
t
t
SCKH
D
D
ACQ
14
A
B
0
0
D
15
A
13
CONVERT
DATA IN
CLK
D
16
A
DIGITAL HOST
12
26
D
27
A
1
D
28
A
0
AD7946