AD7323 Analog Devices, AD7323 Datasheet - Page 16

• Manufacturer Part Number: AD7323
• Description: 500 kSPS, 4-Channel, Software Selectable True bipolar Input, 12-Bit Plus Sign A/D Converter
• Manufacturer: Analog Devices

Specifications of AD7323

• Resolution (bits): 13bit
• # Chan: 4
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: Bip 10V,Bip 2.5V,Bip 5.0V,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7323
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7323 is a fast, 4-channel, 12-bit plus sign, bipolar input,
serial ADC. The AD7323 can accept bipolar input ranges that
include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to
+10 V unipolar input range. A different analog input range can
be programmed on each analog input channel via the on-chip
registers. The AD7323 has a high speed serial interface that can
operate at throughput rates up to 500 kSPS.
The AD7323 requires V
analog input structures. These supplies must be equal to or greater
than the largest analog input range selected. See Table 6 for the
requirements of these supplies for each analog input range. The
AD7323 requires a low voltage 2.7 V to 5.25 V V
power the ADC core.
Table 6. Reference and Supply Requirements for Each
Analog Input Range
Selected
Analog Input
Range (V)
±10
±5
±2.5
0 to +10
It may be necessary to decrease the throughput rate when the
AD7323 is configured with the minimum V
meet the performance specifications (see the Typical Performance
Characteristics section). Figure 31 shows the change in THD as
the V
maximum throughput rate, the THD degrades slightly as V
and V
throughput rate when using minimum V
that there is less degradation of THD and the specified perfor-
mance can be maintained. The degradation is due to an increase
in the on resistance of the input multiplexer when the V
V
change in INL and DNL as the V
For dc performance when operating at the maximum through-
put rate, as the V
typical INL and DNL error remains constant.
SS
supplies are reduced. Figure 18 and Figure 19 show the
DD
SS
are reduced. It may therefore be necessary to reduce the
and V
SS
Reference
Voltage (V)
2.5
3.0
2.5
3.0
2.5
3.0
2.5
3.0
supplies are reduced. For ac performance at the
DD
and V
DD
and V
SS
supply voltages are reduced, the
SS
Full-Scale
Input
Range (V)
±10
±12
±5
±6
±2.5
±3
0 to +10
0 to +12
DD
dual supplies for the high voltage
and V
DD
SS
DD
and V
voltages are varied.
V
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
and V
CC
(V)
CC
SS
SS
supply to
supplies so
supplies to
Minimum
V
±10
±12
±5
±6
±5
±5
+10/AGND
+12/AGND
DD
DD
/V
DD
and
SS
Rev. A | Page 16 of 36
(V)
The analog inputs can be configured as four single-ended
inputs, two true differential inputs, two pseudo differential
inputs, or three pseudo differential inputs. Selection can be
made by programming the mode bits, Mode 0 and Mode 1,
in the control register.
The serial clock input accesses data from the part and provides
the clock source for the successive approximation ADC. The
AD7323 has an on-chip 2.5 V reference. However, the AD7323
can also work with an external reference. On power-up, the
external reference operation is the default option. If the internal
reference is the preferred option, the user must write to the
reference bit in the control register to select the internal refer-
ence operation.
The AD7323 also features power-down options to allow power
savings between conversions. The power-down modes are
selected by programming the on-chip control register, as
described in the Modes of Operation section.
CONVERTER OPERATION
The AD7323 is a successive approximation ADC built around
two capacitive DACs. Figure 23 and Figure 24 show simplified
schematics of the ADC in single-ended mode during the acquisi-
tion and conversion phases, respectively. Figure 25 and Figure 26
show simplified schematics of the ADC in differential mode
during acquisition and conversion phases, respectively. The
ADC is composed of control logic, a SAR, and capacitive DACs.
In Figure 23 (the acquisition phase), SW2 is closed and SW1 is
in Position A, the comparator is held in a balanced condition,
and the sampling capacitor array acquires the signal on the input.
When the ADC starts a conversion (see Figure 24), SW2 opens
and SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
V
V
IN
IN
x
x
Figure 23. ADC Acquisition Phase (Single-Ended)
Figure 24. ADC Conversion Phase (Single-Ended)
AGND
AGND
B
B
A
A
SW1
SW1
C
C
S
S
SW2
SW2
COMPARATOR
COMPARATOR
CAPACITIVE
CAPACITIVE
CONTROL
CONTROL
DAC
LOGIC
DAC
LOGIC