AD7690 Analog Devices, AD7690 Datasheet - Page 21
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AD7690
Manufacturer Part Number
AD7690
Description
Manufacturer
Analog Devices
Datasheet
1.AD7690.pdf
(24 pages)
Specifications of AD7690
Resolution (bits)
18bit
# Chan
1
Sample Rate
400kSPS
Interface
Ser,SPI
Analog Input Type
Diff-Uni
Ain Range
(2Vref) p-p
Adc Architecture
SAR
Pkg Type
CSP,SOP
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CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7690s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7690s is shown in
Figure 42, and the corresponding timing is given in Figure 43.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
SDO
ACQUISITION
SDI
A
t
= SDI
HSCKCNV
CNV
SCK
SDO
A
= 0
B
B
CONVERSION
t
SSCKCNV
t
CONV
t
EN
SDI
t
t
HSDO
DSDO
AD7690
Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing
Figure 42. Chain Mode Without Busy Indicator Connection Diagram
CNV
SCK
A
D
D
1
A
B
17
17
t
SSDISCK
SDO
D
D
2
A
B
16
16
D
D
3
A
B
15
15
Rev. B | Page 21 of 24
t
SCKL
SDI
t
HSDISCK
16
AD7690
CNV
SCK
B
t
D
D
17
CYC
A
B
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7690 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7690s in the chain, provided the
digital host has an acceptable hold time. The maximum conversion
rate may be reduced due to the total readback time.
1
1
ACQUISITION
t
SDO
SCK
t
SCKH
t
D
D
ACQ
18
A
B
0
0
D
19
A
17
CONVERT
DATA IN
CLK
D
20
A
DIGITAL HOST
16
34
D
35
A
1
D
36
A
0
AD7690