AD7690 Analog Devices, AD7690 Datasheet - Page 17

• Manufacturer Part Number: AD7690
• Manufacturer: Analog Devices

Specifications of AD7690

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 400kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7690 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 34, and the corresponding timing is given in
Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
SDI = 1
ACQUISITION
SDO
CNV
SCK
t
CNVH
Figure 35. 3-Wire CS Mode Without Busy Indicator Serial Interface Timing (SDI High)
CONVERSION
t
CONV
VIO
Figure 34. 3-Wire CS Mode Without Busy Indicator
SDI
t
AD7690
EN
CNV
SCK
Connection Diagram (SDI High)
D17
1
Rev. B | Page 17 of 24
t
SDO
HSDO
D16
2
t
CYC
ACQUISITION
high for the maximum possible conversion time to avoid the
generation of the busy signal indicator. When the conversion is
complete, the AD7690 enters the acquisition phase and powers
down. When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the
SCK falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 18
CNV goes high (whichever occurs first), SDO returns to high
impedance.
D15
t
3
ACQ
t
DSDO
CLK
CONVERT
DATA IN
DIGITAL HOST
t
SCKL
t
SCKH
16
t
SCK
17
D1
18
D0
th
SCK falling edge or when
t
DIS
AD7690