AD7766 Analog Devices, AD7766 Datasheet
AD7766
Specifications of AD7766
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AD7766 Summary of contents
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... AD7766/AD7766-1/AD7766-2 provide 24-bit resolution. The combination of exceptional SNR, wide dynamic range, and outstanding dc accuracy make the AD7766/AD7766-1/ AD7766-2 ideally suited for measuring small signal changes over a wide dynamic range. This is particularly suitable for applications where small changes on the input are measured on larger signals ...
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... Parameter and Integral Nonlinearity Parameter, Table 2 ....... 3 Change to Figure 21 and Figure 24 .............................................. 12 Changes to Supply and Reference Voltages Section ................... 16 Changes to Choosing the SCLK Frequency Section .................. 18 Changes to Driving the AD7766 Section .................................... 20 Changes to Single-Ended Signal Source Section ........................ 20 Changes to Figure 40 and Figure 41 ............................................. 20 Added Table 8; Renumbered Sequentially .................................. 20 Change to Figure 42 ...
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... Dynamic Range 2 Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) 2 Total Harmonic Distortion (THD) 2 Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms AD7766-2 2 Dynamic Range 2 Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD Intermodulation Distortion (IMD) Second-Order Terms ...
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... Power-Down Mode Current POWER DISSIPATION AD7766 Operational Power AD7766-1 Operational Power AD7766-2 Operational Power 1 Specifications are for all devices, AD7766, AD7766-1, and AD7766-2. 2 See the Terminology section. Test Conditions/Comments Complete settling Serial 24 bits, twos complement (MSB first +500 μA SINK I = − ...
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... MCLK input, where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum 2 3 MCLK frequency is 1.024 MHz for AD7766 for the AD7766- for the AD7766- common-mode input = V REF Unit ...
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... AD7766 TIMING DIAGRAMS 1 MCLK t 1 DRDY Figure 2. DRDY vs. MCLK Timing Diagram for AD7766 (Decimate by 8 for AD7766-1 (Decimate by 16 for AD7766-2 (Decimate by 32) DRDY SCLK t 7 SDO DRDY SCLK DATA SDO MSB INVALID × n ...
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... DRDY (O) VALID DATA SDO (O) Figure 5. Reset, Synchronization, and Power-Down Timing (For More Information, See the Power-Down, Reset, and Synchronization Section) PART OUT OF POWER-DOWN FILTER RESET BEGINS SAMPLING SETTLING INVALID DATA Rev Page AD7766 t 21 VALID DATA ...
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... AD7766 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter AV to AGND DGND REFGND REF+ REFGND to AGND V to DGND DRIVE AGND IN+, IN– Digital Inputs to DGND Digital Outputs to DGND AGND to DGND Input Current to Any Pin Except ...
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... AD7766/AD7766-1/AD7766-2. See the further details. 13 SCLK Serial Clock Input. The SCLK input provides the serial clock for all serial data transfers with the AD7766/AD7766-1/ AD7766-2 devices. See the AD7766/AD7766-1/AD77662-2 Interface section for further details. 14 MCLK Master Clock Input. The sampling frequency of the AD7766/AD7766-1/AD7766-2 is equal to the MCLK frequency. ...
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... FREQUENCY (Hz) Figure 10. AD7766 FFT, 1 kHz, −6 dB Input Tone 4k 8k 12k 16k 20k 24k 28k FREQUENCY (Hz) Figure 11. AD7766-1 FFT, 1 kHz, −6 dB Input Tone 4k 8k 12k FREQUENCY (Hz) Figure 12. AD7766-2 FFT, 1 kHz, −6 dB Input Tone 64k 32k 1 6k ...
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... FREQUENCY (Hz) Figure 13. AD7766 FFT, 1 kHz, −60 dB Input Tone 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 12k 16k 20k 24k FREQUENCY (Hz) Figure 14. AD7766-1 FFT, 1 kHz, −60 dB Input Tone 0 – ...
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... 140 130 120 110 100 0 10k 20k 30k f (Hz) NOISE Figure 21. AD7766 Power Supply Sensitivity vs. Supply Ripple Frequency (f ) with Decoupling Capacitors NOISE 700k 800k 900k 1 M Figure 22. AD7766 CMRR vs. Common-Mode Ripple Frequency (f 700k 800k 900k 1M V DRIVE 40k ...
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... CODES Figure 26. AD7766/AD7766-1/AD7766-2 24-Bit DNL –3 –6 –9 –12 –15 0 2,097,152 Figure 27. AD7766/AD7766-1/AD7766-2 24-Bit INL 16,777,216 14,680,064 Rev Page AD7766 4,194,304 8,388,608 12,582,912 16,777,216 6,291,456 10,485,760 14,680,064 24-BIT CODES ...
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... The AD7766 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies ...
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... DATA STREAM ( for AD7766 for AD7766- for AD7766-2) Table 6 shows the three available models of the AD7766, listing the change in output data rate relative to the order of decimation rate implemented. This brings into focus the trade-off that exists ...
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... The AD7766/AD7766-1/AD7766-2 operate from a 2.5 V supply applied to the DV operate between 1.7 V and 3.6 V. The AD7766/AD7766-1/ AD7766-2 operate from a reference input in the range of 2 × AV supply voltage but a 2.5 V supply can also be used. When using reference, the recommended reference devices are the ADR445, ADR435, or ADR425 ...
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... data read cycle. The CS signal is a gate for the SDO pin and allows many AD7766/AD7766-1/ AD7766-2 devices to share the same serial bus. It acts as an instruction signal to each of these devices indicating permission to use the bus. When CS is logic high, the SDO line of the AD7766/AD7766-1/AD7766-2 is tristated ...
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... An example of a daisy chain of four AD7766 devices is shown in Figure 36 and Figure 37. In the case illustrated in Figure 36, the output of the AD7766 labeled A is the output of the full daisy chain. The last device in the chain (the AD7766 labeled D) has its serial data input (SDI) pin connected to ground. All the devices in the chain must use common MCLK, SCLK and SYNC / PD signals ...
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... SCLK SCLK AD7766 (A) SDO (A) SDI (A) = SDO (B) AD7766 (B) AD7766 (C) SDI (B) = SDO (C) SDI (C) = SDO (D) AD7766 (D) Figure 37. Daisy-Chain Timing Diagram ( for AD7766 for AD7766- for AD7766-2) When Driving the AD7766 MCLK DRDY (A) CS SDO (A) MSB (A) SCLK t 16 MSB (B) SDI (A) = SDO (B) ...
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... LSB voltage. Figure 39 shows the maximum inputs to the AD7766. DIFFERENTIAL SIGNAL SOURCE An example of recommended driving circuitry that can be used in conjunction with the AD7766 is shown in Figure 40. Figure 40 shows how the ADA4841-1 device can be used to drive an input to the AD7766 from a differential source. Each of the differential paths is driven by an ADA4841-1 device ...
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... Both the digital and analog currents scale as the MCLK frequency is reduced. The actual throughput equals the MCLK frequency applied divided by the decimation rate employed by the device in use. For instance, operating the AD7766 device with an MCLK of 800 kHz results in an output data rate of 100 kHz due to the decimate-by-8 filtering. ...
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... V. result is available and the input is switched once more. DD The AD7766 filter settling time equals 74 divided by the output data rate in use. The maximum switching frequency in a multi- plexed application is, therefore, 1/(74/ODR), where the output data rate (ODR function of the applied MCLK frequency and the decimation rate employed by the device in question ...
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... Temperature Range AD7766BRUZ −40°C to +105°C AD7766BRUZ-RL7 −40°C to +105°C AD7766BRUZ-1 −40°C to +105°C AD7766BRUZ-1-RL7 −40°C to +105°C AD7766BRUZ-2 −40°C to +105°C AD7766BRUZ-2-RL7 −40°C to +105°C EVAL-AD7766EDZ EVAL-AD7766-1EDZ EVAL-AD7766-2EDZ EVAL-CED1Z RoHS Compliant Part. 5.10 5.00 4. 4.50 6.40 4 ...
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... AD7766 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06449-0-4/10(C) Rev Page ...