AD7764 Analog Devices, AD7764 Datasheet - Page 6

• Manufacturer Part Number: AD7764
• Description: 24-Bit, 312 kSPS, 109 dB Sigma Delta ADC with On-Chip Buffers and Serial Interface
• Manufacturer: Analog Devices

Specifications of AD7764

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: 40MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: 6.5 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7764
TIMING SPECIFICATIONS
AV
Table 3.
Parameter
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
MCLK
ICLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R MIN
R HOLD
R SETUP
S MIN
S HOLD
S SETUP
This is the maximum time FSI can be held low when writing to an individual device (a device that is not daisy-chained).
1
DD
1 = DV
DD
= 2.5 V, AV
Limit at T
500
40
250
20
1 × t
1 × t
1
2
8
40
9.5
2
32 × t
12
1 × t
32 × t
12
12
0
1 × t
5
5
4 × t
5
5
ICLK
ICLK
SCO
MCLK
MCLK
SCO
SCO
DD
2 = AV
MIN
, T
MAX
DD
3 = AV
DD
4 = 5 V, V
Unit
kHz min
MHz max
kHz min
MHz max
typ
typ
ns typ
ns typ
ns max
ns min
ns max
ns typ
max
ns min
min
max
ns min
ns min
ns max
min
ns min
ns min
min
ns min
ns min
REF
+ = 4.096 V, T
Rev. A | Page 6 of 32
Description
Applied master clock frequency
Internal modulator clock derived from MCLK
SCO high period
SCO low period
SCO rising edge to FSO falling edge
Data access time, FSO falling edge to data active
MSB data access time, SDO active to SDO valid
Data hold time (SDO valid to SCO rising edge)
Data access time (SCO rising edge to SDO valid)
SCO rising edge to FSO rising edge
FSO low period
Setup time from FSI falling edge to SCO falling edge
FSI low period
FSI low period
SDI setup time for the first data bit
SDI setup time
SDI hold time
Minimum time for a valid RESET pulse
Minimum time between the MCLK rising edge and RESET rising edge
Minimum time between the RESET rising edge and MCLK rising edge
Minimum time for a valid SYNC pulse
Minimum time between the MCLK falling edge and SYNC rising edge
Minimum time between the SYNC rising edge and MCLK falling edge
A
= 25°C, C
LOAD
= 25 pF.