AD7764 Analog Devices, AD7764 Datasheet
AD7764
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AD7764 Summary of contents
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... The external clock frequency applied to the AD7764 determines the sample rate, filter corner frequencies, and output word rate. The AD7764 device boasts a full band on-board FIR filter. The full stop-band attenuation of the filter is achieved at the Nyquist frequency. This feature offers increased protection from signals that lie above the Nyquist frequency being aliased back into the input signal bandwidth ...
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... Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 8 Changes to Typical Performance Characteristics Section, Introductory Text............................................................................ 11 Changes to Σ-Δ Modulation and Digital Filtering Section ....... 16 Added AD7764 Antialias Protection Section ............................. 17 Changes to Figure 35 ...................................................................... 19 Synchronization ...........................................................................22 Overrange Alerts .........................................................................22 Power Modes ................................................................................23 Decimation Rate Pin ...................................................................23 Daisy Chaining ................................................................................24 Reading Data in Daisy-Chain Mode ...
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... Differential amplifier inputs shorted Input amplitude = −0.5 dB Input amplitude = −0.5 dB Input amplitude = −6 dB Input amplitude = −6 dB Input amplitude = −6 dB 50.3 kHz Second-order terms Third-order terms Rev Page AD7764 = 25°C, normal power mode, using A 1 Specification Unit 115 dB typ 110 dB min 113.4 ...
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... AD7764 Parameter Decimate 64× Normal Power Mode Dynamic Range 2 Signal-to-Noise Ratio (SNR) Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) Intermodulation Distortion (IMD) Low Power Mode Dynamic Range Signal-to-Noise Ratio (SNR) 2 Spurious-Free Dynamic Range (SFDR) Total Harmonic Distortion (THD) ...
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... SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 3 Output data rate (ODR) = [(MCLK/2)]/decimation rate. That is, the maximum ODR for AD7764 = [(40 MHz)/2)/64] = 312.5 kHz. 4 Tested with a 400 µA load current. ...
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... AD7764 TIMING SPECIFICATIONS 2 Table 3. Parameter Limit MIN MAX f 500 MCLK 40 f 250 ICLK × ICLK t 1 × ICLK 9 × SCO t 12 ...
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... RA12 RA11 RA10 RA9 RA8 Figure 3. AD7764 Register Write ≥8 × t SCO NEXT DATA READ FOLLOWING THE WRITE TO CONTROL REGISTER INSTRUCTION Figure 4. AD7764 Status Register Read Cycle Rev Page ST3 ST2 ST1 ST0 0 0 RA1 RA0 D15 D14 D1 STATUS REGISTER DON’ ...
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... AD7764 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameter GND GND GND A+, V A− to GND − to GND Digital Input Voltage to GND GND 3 REF Input Current to Any Pin Except Supplies ...
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... SDO Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an SCO rising edge and is valid on the falling edge. See the AD7764 Interface section for further details. 13 SDI Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched. ...
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... FSI Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first data bit is latched in on the next SCO falling edge. See the AD7764 Interface section for further details. 15 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system ...
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... Linearity plots measured 25k 50k 75k 100k 125k FREQUENCY (Hz) 64× Decimation Rate 0 10k 20k 30k 40k 50k 60k FREQUENCY (Hz) 128× Decimation Rate 0 5k 10k 15k 20k 25k 30k FREQUENCY (Hz) 256× Decimation Rate AD7764 150k 70k 35k ...
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... AD7764 0 –25 –50 –75 –100 –125 –150 –175 0 50k 100k FREQUENCY (Hz) Figure 12. Normal Power Mode, FFT,1 kHz, −6 dB Input Tone, 64× Decimation Rate 0 –25 –50 –75 –100 –125 –150 –175 0 25k 50k FREQUENCY (Hz) Figure 13. Normal Power Mode, FFT,1 kHz, −6 dB Input Tone, 128× ...
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... MCLK FREQUENCY (MHz) 128× Decimation Rate MCLK FREQUENCY (MHz) 256× Decimation Rate AD7764 ...
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... AD7764 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 6k 10k 15k 20k 25k 30k 35k 40k CODE Figure 24. DNL Plot 0.00300 0.00225 0.00150 0.00075 0 –0.00075 –0.00150 –0.00225 –0.00300 6k 10k 15k 20k 25k 30k 35k 40k 16-BIT CODE SCALING Figure 25. Normal Power Mode INL ...
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... The AD7764 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies ...
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... ICLK decimation rate used. The AD7764 employs three FIR filters in series. By using different combinations of decimation ratios, data can be obtained from the AD7764 at three data rates. The first filter receives data from the modulator at ICLK MHz where it is decimated 4× ...
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... MCLK frequency applied. When using low power mode, the modulator sample rate is MCLK/4. Taking as an example the AD7764 in normal power and in decimate × 128 mode, the first possible alias frequency is at the ICLK frequency minus the pass band of the digital filter (see Figure 33) ...
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... Modulator This means that a maximum of ±3.2768 V p-p full-scale can be applied to each of the AD7764 modulator inputs (Pin 5 and Pin 6), with the AD7764 being specified with an input −0.5 dB down from full scale (−0.5 dBFS). The AD7764 modulator inputs must have a common-mode input of 2.048 V. ...
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... ON-CHIP DIFFERENTIAL AMPLIFIER The AD7764 contains an on-board differential amplifier that is recommended to drive the modulator input pins. Pin 1, Pin 2, Pin 3, and Pin 4 on the AD7764 are the differential input and output pins of the amplifier. The external components and R , are placed around Pin 1 through Pin 6 to create ...
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... ANALOG MODULATOR voltage of 2.048 V and adhere to the amplitudes as described in the AD7764 Input Structure section. An example of a typical circuit to drive the AD7764 for applica- tions requiring excellent ac and dc performance is shown in Figure 40. Either the the AD7764 modulator inputs directly. Best practice is to short the differential amplifier inputs to ground through the typical input resistors and leave the typical ...
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... Don’t care. If the DEC_RATE 1 bit is set to 1, AD7764 is in decimate 128× mode. READING STATUS AND OTHER REGISTERS The AD7764 features a gain correction register, an overrange register, and a read-only status register. To read back the contents of these registers, the user must first write to the control register of the device and set the bit that corresponds to the register to be read ...
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... In the case of a system with multiple AD7764s, connect common MCLK, SYNC and RESET signals to each AD7764. The AD7764 SYNC pin is polled by the falling edge of MCLK. The AD7764 device goes into SYNC when an MCLK falling edge senses that the SYNC input signal is logic low. At this point, the digital filter sequencer is reset to 0 ...
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... All internal circuitry is reset. Apply a RESET pulse to the AD7764 after initial power-up of the device. The AD7764 RESET pin is polled by the rising edge of MCLK. The AD7764 device goes into reset when an MCLK rising senses the RESET input signal to be logic low. AD7764 comes out of RESET on the first MCLK rising edge that senses RESET to be logic high ...
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... Referring to Figure 45, note that the SDO line of AD7764 (A) provides the output data from the chain of AD7764 converters. Also, note that for the last device in the chain, AD7764 (D), the SDI pin is connected to ground. All of the devices in the chain must use common MCLK and SYNC signals ...
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... SCO periods indicates to the AD7764 device that there are more devices further on in the chain. This means that the AD7764 directs data that is input on the SDI pin to its SDO pin. This ensures that data is passed to the next device in the chain ...
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... AD7764 CLOCKING THE AD7764 The AD7764 requires an external low jitter clock source. This signal is applied to the MCLK pin. An internal clock signal (ICLK) is derived from the MCLK input signal. The ICLK controls the internal operation of the AD7764. The maximum ICLK frequency is 20 MHz. To generate the ICLK, ...
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... AV 4 (Pin 25) DD • (Pin 24) DD • (Pin 21 layout decoupling scheme for these supplies, which connect to the right side of the AD7764, is shown in Figure 51. Note the star-point ground created at Pin 23 (PIN 25) GND AV PIN 23 V STAR-POINT GND AV ...
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... Values for gain and overrange thresholds can be written to or read from the respective registers at this stage. BIAS RESISTOR SELECTION The AD7764 requires a resistor to be connected between the RESET is R and AGNDx pins. The resistor value should be selected to BIAS give a current of 25 µ ...
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... AD7764 REGISTERS The AD7764 has a number of user-programmable registers. The control register is used to set the functionality of the on-chip buffer and differential amplifier and provides the option to power down the AD7764. There are also digital gain and overrange threshold registers. Writing to these registers involves writing the register address followed by a 16-bit data-word. The register addresses, details of individual bits, and default values are provided in this section ...
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... AD7764 GAIN REGISTER—ADDRESS 0x0004 Non-Bit-Mapped, Default Value 0xA000 The gain register is scaled such that 0x8000 corresponds to a gain of 1.0. The default value of this register is 1.25 (0xA000). This results in a full-scale digital output when the input tying in with the maximum analog input range of REF ± ...
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... SEATING 0.19 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 54. 28-Lead Thin Shrink Small Outline [TSSOP] (RU-28) Dimensions shown in millimeters Package Description 28-Lead Thin Shrink Small Outline [TSSOP] 28-Lead Thin Shrink Small Outline [TSSOP] Evaluation Board Rev Page 6.40 BSC 8 ° 0.75 0 ° 0.60 0.45 Package Option RU-28 RU-28 AD7764 ...
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... AD7764 NOTES ©2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06518-0-11/09(A) Rev Page ...