AD7367-5 Analog Devices, AD7367-5 Datasheet - Page 20

• Manufacturer Part Number: AD7367-5
• Description: True Bipolar Input, 14-Bit, 2-Channel, Simultaneous Sampling SAR ADC
• Manufacturer: Analog Devices

Specifications of AD7367-5

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 500kSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V,Uni 10V
• Adc Architecture: SAR
• Pkg Type: SOP

AD7366-5/AD7367-5
MODES OF OPERATION
The mode of operation for the AD7366-5/AD7367-5 is selected
by the (logic) state of the CNVST signal at the end of a conver-
sion. There are two possible modes of operation: normal mode
and shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
Normal mode is intended for applications needing fast
throughput rates because the user does not have to worry
about any power-up times (with the AD7366-5/AD7367-5
remaining fully powered at all times). Figure 22 shows the
normal mode of operation for the AD7366-5, while Figure 23
illustrates normal mode for the AD7367-5.
The conversion is initiated on the falling edge of CNVST as
described in the
the part remains fully powered up at all times,
at a logic high state prior to the BUSY signal going low. If
CNVST is at a logic low state when the BUSY signal goes low,
the analog circuitry powers down and the part ceases converting.
Circuit Information
CNVST
CNVST
BUSY
BUSY
SCLK
SCLK
CS
CS
t
t
2
2
section. To ensure that
SERIAL READ OPERATION
t
SERIAL READ OPERATION
t
1
1
CNVST must be
Figure 22. Normal Mode Operation for the AD7366-5
Figure 23. Normal Mode Operation for the AD7367-5
t
t
CONVERT
CONVERT
Rev. A | Page 20 of 28
1
1
t
t
3
3
The BUSY signal remains high for the duration of the conversion.
The CS pin must be brought low to bring the data bus out of
three-state; subsequently 12 SCLK cycles are required to read
the conversion result from the AD7366-5, while 14 SCLK cycles
are required to read from the AD7367-5. The D
to three-state only when CS is brought high. If CS is left low for
a further 12 SCLK cycles for the AD7366-5 or 14 SCLK cycles
for the AD7367-5, the result from the other on-chip ADC is
also accessed on the same D
Figure 28
After 24 SCLK cycles have elapsed for the AD7366-5 and 28 SCLK
cycles have elapsed for the AD7367-5, the D
three-state when CS is brought high (not on the 24
falling edge). If CS is brought high prior to this, the D
returns to three-state at that point. Thus, CS must be brought
high once the read is completed because the bus does not
automatically return to three-state upon completion of the
dual result read.
Once a data transfer is complete and D
returned to three-state, another conversion can be initiated after
the quiet time, t
(see the
QUIET
t
t
QUIET
QUIET
Serial Interface
, has elapsed by bringing CNVST low again.
14
12
OUT
line, as shown in
section).
OUT
A and D
OUT
OUT
line returns to
Figure 27
th
OUT
or 28
lines return
B have
OUT
th
line
SCLK
and